We certainly want this:

commit 71c751f2a43fa03fae3cf5f0067ed3001a397013
Author: Mark Rutland <mark.rutl...@arm.com>
Date:   Mon Apr 23 11:41:33 2018 +0100

    arm64: add sentinel to kpti_safe_list
    
    We're missing a sentinel entry in kpti_safe_list. Thus 
is_midr_in_range_list()
    can walk past the end of kpti_safe_list. Depending on the contents of 
memory,
    this could erroneously match a CPU's MIDR, cause a data abort, or other bad
    outcomes.
    
    Add the sentinel entry to avoid this.
    
    Fixes: be5b299830c63ed7 ("arm64: capabilities: Add support for checks based 
on a list of MIDRs")
    Signed-off-by: Mark Rutland <mark.rutl...@arm.com>
    Reported-by: Jan Kiszka <jan.kis...@siemens.com>
    Tested-by: Jan Kiszka <jan.kis...@siemens.com>
    Reviewed-by: Suzuki K Poulose <suzuki.poul...@arm.com>
    Cc: Catalin Marinas <catalin.mari...@arm.com>
    Cc: Suzuki K Poulose <suzuki.poul...@arm.com>
    Cc: Will Deacon <will.dea...@arm.com>
    Signed-off-by: Will Deacon <will.dea...@arm.com>

diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index 536d572e5596..9d1b06d67c53 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -868,6 +868,7 @@ static bool unmap_kernel_at_el0(const struct 
arm64_cpu_capabilities *entry,
        static const struct midr_range kpti_safe_list[] = {
                MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2),
                MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN),
+               { /* sentinel */ }
        };
        char const *str = "command line option";

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  Cavium ThunderX CN88XX Panic : Unknown reason

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