Looking through the code in it87_wdt.c it appears that the open/close of
the timer is performed by writing to the configuration registers that
Cinquero identified, however, that is not how the refresh is performed!
Looking at this part of the code:
/* watchdog timer handling */
static void wdt_keepalive(void)
{
if (test_bit(WDTS_USE_GP, &wdt_status))
inb(base);
else
/* The timer reloads with around 5 msec delay */
outb(0x55, CIR_DR(base));
set_bit(WDTS_KEEPALIVE, &wdt_status);
}
And the page 8.11.6 from the manual (JPEG image posted by Cinquero) it
seems that the watchdog, once armed, is supposed to be reset via a "CIR
Interrupt" that presumably is generated by writing 0x55 to the CIR's
base address (default is from #define CIR_BASE 0x0208).
So has anyone any idea of with the CIR actually is, or how it works?
The alternative seems to be a code change so the wdt_keepalive() call
re-writes the timer, but I am guessing there was a good reason for doing
this way originally (e.g. time involved in slow I/O register access or
similar).
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https://bugs.launchpad.net/bugs/932381
Title:
IT87 watchdog timer driver not working
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