A short overview of where posbuf is used in hda_intel.c:
In azx_init_chip():
azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
azx_writel(chip, DPUBASE, upper_32bit(chip->posbuf.addr));
In azx_setup_controller():
// enable the position buffer
if (! (azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
In azx_init_stream():
azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
In azx_pcm_pointer():
pos = le32_to_cpu(*azx_dev->posbuf);
In azx_create():
snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
chip->num_streams * 8, &chip->posbuf)) < 0)
So, chip->posbuf is a dma buffer that contains stream pointers (DMA
Position Base Address), which are initialised in azx_init_stream().
Addresses must be 128-byte aligned. When the lowest bit is set, "the
controller will write the DMA positions of each of the DMA engines to
the buffer in the main memory periodically (typically once per frame).
Software can use this value to know what data in memory is valid data."
(18.2.31 DPLBASE) - it seems that the hardware does report back the
position.
Note 1 mentioned in 18.2.6 GCTL struck me (about reset bit): "The
CORB/RIRB RUN bits and all stream RUN bits must be verified cleared to 0
before writing a 0 to this bit in order to assure a clean re-start." I
don't see this happening in/before azx_reset().
--
snd-hda-intel: distorted sound after resume, until the module is reloaded
https://bugs.launchpad.net/bugs/100114
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