Change CLK_TOP_CLK13M rate from 130_000_000 to 13_000_000 and
CLK_TOP_CLK26M rate from 260_000_000 to 26_000_000. As the names
suggest, these clocks are 13/26 MHz, not 130/260 MHz.
Fixes: 5e9bbbdab003 ("clk: mediatek: mt8188: add missing fixed clock")
Fixes: 11f3cc46322a ("clk: mediatek: add MT8188 clock driver")
Signed-off-by: David Lechner <[email protected]>
---
In v1 I said that this should go into master, but I found that there
were other fixes that went into next already instead of master. Applying
the v1 patch would cause a merge conflict because of this. So I've
changed the patch to apply to next to avoid merge conflict. This driver
and the board that depends on it isn't really usable in master anyway
so I think this should be OK to not fix it in master.
And I found that next had the same bug on CLK13M, so I've updated the
patch to fix both.
---
Changes in v2:
- Added fix for CLK_TOP_CLK13M as well.
- Link to v1:
https://lore.kernel.org/r/[email protected]
---
drivers/clk/mediatek/clk-mt8188.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/mediatek/clk-mt8188.c
b/drivers/clk/mediatek/clk-mt8188.c
index b720eec8ba7..803330717c6 100644
--- a/drivers/clk/mediatek/clk-mt8188.c
+++ b/drivers/clk/mediatek/clk-mt8188.c
@@ -97,8 +97,8 @@ static const struct mtk_fixed_clk top_fixed_clks[] = {
FIXED_CLK0(CLK_TOP_466M_FMEM, 533000000),
FIXED_CLK0(CLK_TOP_PEXTP_PIPE, 250000000),
FIXED_CLK0(CLK_TOP_DSI_PHY, 500000000),
- FIXED_CLK0(CLK_TOP_CLK13M, 130000000),
- FIXED_CLK0(CLK_TOP_CLK26M, 260000000),
+ FIXED_CLK0(CLK_TOP_CLK13M, 13000000),
+ FIXED_CLK0(CLK_TOP_CLK26M, 26000000),
FIXED_CLK0(CLK_TOP_CLK32K, 32000),
};
---
base-commit: c0ca147ac6228949a6d6497531c9f2f4a0dc6c67
change-id: 20260304-clk-mtk-fix-mt8188-rates-9c733a841d56
Best regards,
--
David Lechner <[email protected]>
