From: Jonas Schwöbel <[email protected]> When PWM config was updated the clock was restarted which caused loss of previous configuration of other channels. Further this fixes a bug/hang that can happen when set_enable was called before set_config.
Signed-off-by: Jonas Schwöbel <[email protected]> Signed-off-by: Svyatoslav Ryhel <[email protected]> --- drivers/pwm/tegra_pwm.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/drivers/pwm/tegra_pwm.c b/drivers/pwm/tegra_pwm.c index e3f1417f2ad..7105d6db90d 100644 --- a/drivers/pwm/tegra_pwm.c +++ b/drivers/pwm/tegra_pwm.c @@ -19,7 +19,6 @@ static int tegra_pwm_set_config(struct udevice *dev, uint channel, { struct tegra_pwm_priv *priv = dev_get_priv(dev); struct pwm_ctlr *regs = priv->regs; - const u32 pwm_max_freq = dev_get_driver_data(dev); uint pulse_width; u32 reg; @@ -27,8 +26,6 @@ static int tegra_pwm_set_config(struct udevice *dev, uint channel, return -EINVAL; debug("%s: Configure '%s' channel %u\n", __func__, dev->name, channel); - clock_start_periph_pll(PERIPH_ID_PWM, CLOCK_ID_PERIPH, pwm_max_freq); - pulse_width = duty_ns * 255 / period_ns; reg = pulse_width << PWM_WIDTH_SHIFT; @@ -63,6 +60,15 @@ static int tegra_pwm_of_to_plat(struct udevice *dev) return 0; } +static int tegra_pwm_probe(struct udevice *dev) +{ + const u32 pwm_max_freq = dev_get_driver_data(dev); + + clock_start_periph_pll(PERIPH_ID_PWM, CLOCK_ID_PERIPH, pwm_max_freq); + + return 0; +} + static const struct pwm_ops tegra_pwm_ops = { .set_config = tegra_pwm_set_config, .set_enable = tegra_pwm_set_enable, @@ -80,5 +86,6 @@ U_BOOT_DRIVER(tegra_pwm) = { .of_match = tegra_pwm_ids, .ops = &tegra_pwm_ops, .of_to_plat = tegra_pwm_of_to_plat, + .probe = tegra_pwm_probe, .priv_auto = sizeof(struct tegra_pwm_priv), }; -- 2.51.0
