Hi Alif, Since 2025.05 to the latest master. I do not have any issue as you mentioned in this patch. Both RD/WR are used on the FPGA2SDRAM SDRAM2FPGA. I tested 256 AXI3 or split 128 AXI3 x2 which is the maximum that GEN5 Cyclone can support.
Not too sure what is missing from first place? Thanks, Brian
