On February 6, 2026 thus sayeth Anshul Dalal: > On Tue Feb 3, 2026 at 7:09 PM IST, Bryan Brattlof wrote: > > On January 22, 2026 thus sayeth Anshul Dalal: > >> This patch refactors the nodes in each board's R5 device-tree to common > >> SoC level dtsi. No functional change is intended from this patch. > >> > >> Signed-off-by: Anshul Dalal <[email protected]> > >> --- > > > > ... > > > >> diff --git a/arch/arm/dts/k3-am625-r5.dtsi > >> b/arch/arm/dts/k3-am625-r5.dtsi > >> new file mode 100644 > >> index 00000000000..c509857ac5d > >> --- /dev/null > >> +++ b/arch/arm/dts/k3-am625-r5.dtsi > >> @@ -0,0 +1,88 @@ > >> +// SPDX-License-Identifier: GPL-2.0 > >> +/* > >> + * Copyright (C) 2026 Texas Instruments Incorporated - https://www.ti.com/ > >> + */ > >> + > >> +/ { > >> + aliases { > >> + tick-timer = &main_timer0; > >> + remoteproc0 = &sysctrler; > >> + remoteproc1 = &a53_0; > >> + serial0 = &wkup_uart0; > >> + serial3 = &main_uart1; > >> + }; > >> + > >> + a53_0: a53@0 { > >> + compatible = "ti,am654-rproc"; > >> + reg = <0x00 0x00a90000 0x00 0x10>; > >> + power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>, > >> + <&k3_pds 135 TI_SCI_PD_EXCLUSIVE>, > >> + <&k3_pds 166 TI_SCI_PD_EXCLUSIVE>; > >> + resets = <&k3_reset 135 0>; > >> + clocks = <&k3_clks 61 0>, <&k3_clks 135 0>; > >> + clock-names = "gtc", "core"; > >> + assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>; > >> + assigned-clock-parents = <&k3_clks 61 2>; > >> + assigned-clock-rates = <200000000>, <1200000000>; > > > > I wonder if it is time to drop the A53s to 300MHz (the slowest we sell > > binned parts at) and let the speed grade detection logic speed it up at > > runtime once we know it is safe to do so. > > I had actually recently worked on modifying the clock rates at R5 SPL > stage based on the detected speed grade of the SoC, check the commit > 65a6b83a9b7f ("mach-k3: refactor A53 speed grade clock-rate fixup"). > > Currently we support runtime configuration of clocks based on the speed > grade for AM62a, AM62p, AM62x and AM64x. We can expand the support to > other SoCs in the future. > > However I do agree that the default clock-rate in the A53/A72 node > should be based on the lowest possible speed grade however doing so is > out of the scope for this patch where I tried to keep functional changes > to a minimum.
Sure but this patch assumes all the minimums are the same for all SoCs. Otherwise we brake this out into their individual files again. Anywho the more I look into this the more the clocks are all wrong which this patch didn't cause. Just something I noticed reviewing. ~Bryan
