Update the DDR Configurations for AM64x EVM according to the SysConfig DDR Configuration tool v0.10.32. [1]
[1] https://dev.ti.com/tirex/content/Processor_DDR_Config_0.10.32.0000/docs/REVISION_HISTORY.html Signed-off-by: Santhosh Kumar K <[email protected]> --- arch/arm/dts/k3-am64-evm-ddr4-1600MTs.dtsi | 117 +++++++++++---------- 1 file changed, 59 insertions(+), 58 deletions(-) diff --git a/arch/arm/dts/k3-am64-evm-ddr4-1600MTs.dtsi b/arch/arm/dts/k3-am64-evm-ddr4-1600MTs.dtsi index 1b5fabc3dd16..a35bd349c78a 100644 --- a/arch/arm/dts/k3-am64-evm-ddr4-1600MTs.dtsi +++ b/arch/arm/dts/k3-am64-evm-ddr4-1600MTs.dtsi @@ -1,19 +1,20 @@ // SPDX-License-Identifier: GPL-2.0+ /* * This file was generated with the - * AM64x SysConfig DDR Configuration Tool for AM64x, AM625, AM623, AM62Ax, AM62Px v0.10.02 - * Tue Sep 17 2024 11:01:31 GMT+0530 (India Standard Time) + * AM64x SysConfig DDR Configuration Tool for AM64x, AM625, AM623, AM62Ax, AM62Px, AM62Dx, AM62Lx v0.10.32 + * Fri Jan 30 2026 13:47:49 GMT+0530 (India Standard Time) * DDR Type: DDR4 * Frequency = 800MHz (1600MTs) * Density: 16Gb * Number of Ranks: 1 - */ +*/ #define DDRSS_PLL_FHS_CNT 6 #define DDRSS_PLL_FREQUENCY_1 400000000 #define DDRSS_PLL_FREQUENCY_2 400000000 #define DDRSS_SDRAM_IDX 15 #define DDRSS_REGION_IDX 15 +#define DDRSS_TOOL_VERSION "0.10.32" #define DDRSS_CTL_0_DATA 0x00000A00 #define DDRSS_CTL_1_DATA 0x00000000 @@ -53,12 +54,12 @@ #define DDRSS_CTL_35_DATA 0x00000000 #define DDRSS_CTL_36_DATA 0x00000000 #define DDRSS_CTL_37_DATA 0x00000000 -#define DDRSS_CTL_38_DATA 0x0400091C -#define DDRSS_CTL_39_DATA 0x1C1C1C1C -#define DDRSS_CTL_40_DATA 0x0400091C -#define DDRSS_CTL_41_DATA 0x1C1C1C1C -#define DDRSS_CTL_42_DATA 0x0400091C -#define DDRSS_CTL_43_DATA 0x1C1C1C1C +#define DDRSS_CTL_38_DATA 0x0000091C +#define DDRSS_CTL_39_DATA 0x18181818 +#define DDRSS_CTL_40_DATA 0x0000091C +#define DDRSS_CTL_41_DATA 0x18181818 +#define DDRSS_CTL_42_DATA 0x0000091C +#define DDRSS_CTL_43_DATA 0x18181818 #define DDRSS_CTL_44_DATA 0x05050404 #define DDRSS_CTL_45_DATA 0x00002706 #define DDRSS_CTL_46_DATA 0x0602001D @@ -71,13 +72,13 @@ #define DDRSS_CTL_53_DATA 0x07001D0B #define DDRSS_CTL_54_DATA 0x00180807 #define DDRSS_CTL_55_DATA 0x0400DB60 -#define DDRSS_CTL_56_DATA 0x07070009 +#define DDRSS_CTL_56_DATA 0x07070005 #define DDRSS_CTL_57_DATA 0x00001808 #define DDRSS_CTL_58_DATA 0x0400DB60 -#define DDRSS_CTL_59_DATA 0x07070009 +#define DDRSS_CTL_59_DATA 0x07070005 #define DDRSS_CTL_60_DATA 0x00001808 #define DDRSS_CTL_61_DATA 0x0400DB60 -#define DDRSS_CTL_62_DATA 0x03000009 +#define DDRSS_CTL_62_DATA 0x03000005 #define DDRSS_CTL_63_DATA 0x0D0C0002 #define DDRSS_CTL_64_DATA 0x0D0C0D0C #define DDRSS_CTL_65_DATA 0x01010000 @@ -102,8 +103,8 @@ #define DDRSS_CTL_84_DATA 0x00000000 #define DDRSS_CTL_85_DATA 0x00000000 #define DDRSS_CTL_86_DATA 0x00000000 -#define DDRSS_CTL_87_DATA 0x00090009 -#define DDRSS_CTL_88_DATA 0x00000009 +#define DDRSS_CTL_87_DATA 0x00050005 +#define DDRSS_CTL_88_DATA 0x00000005 #define DDRSS_CTL_89_DATA 0x00000000 #define DDRSS_CTL_90_DATA 0x00000000 #define DDRSS_CTL_91_DATA 0x00000000 @@ -171,8 +172,8 @@ #define DDRSS_CTL_153_DATA 0x00000000 #define DDRSS_CTL_154_DATA 0x00000000 #define DDRSS_CTL_155_DATA 0x00000000 -#define DDRSS_CTL_156_DATA 0x080C0000 -#define DDRSS_CTL_157_DATA 0x080C080C +#define DDRSS_CTL_156_DATA 0x08080000 +#define DDRSS_CTL_157_DATA 0x08080808 #define DDRSS_CTL_158_DATA 0x00000000 #define DDRSS_CTL_159_DATA 0x07010A09 #define DDRSS_CTL_160_DATA 0x000E0A09 @@ -251,12 +252,12 @@ #define DDRSS_CTL_233_DATA 0x00000000 #define DDRSS_CTL_234_DATA 0x00000000 #define DDRSS_CTL_235_DATA 0x00000000 -#define DDRSS_CTL_236_DATA 0x00001401 -#define DDRSS_CTL_237_DATA 0x00001401 -#define DDRSS_CTL_238_DATA 0x00001401 -#define DDRSS_CTL_239_DATA 0x00001401 -#define DDRSS_CTL_240_DATA 0x00001401 -#define DDRSS_CTL_241_DATA 0x00001401 +#define DDRSS_CTL_236_DATA 0x00001400 +#define DDRSS_CTL_237_DATA 0x00001400 +#define DDRSS_CTL_238_DATA 0x00001400 +#define DDRSS_CTL_239_DATA 0x00001400 +#define DDRSS_CTL_240_DATA 0x00001400 +#define DDRSS_CTL_241_DATA 0x00001400 #define DDRSS_CTL_242_DATA 0x00000493 #define DDRSS_CTL_243_DATA 0x00000493 #define DDRSS_CTL_244_DATA 0x00000493 @@ -385,9 +386,9 @@ #define DDRSS_CTL_367_DATA 0x00000000 #define DDRSS_CTL_368_DATA 0x00000000 #define DDRSS_CTL_369_DATA 0x00000000 -#define DDRSS_CTL_370_DATA 0x0C000000 -#define DDRSS_CTL_371_DATA 0x060C0606 -#define DDRSS_CTL_372_DATA 0x06060C06 +#define DDRSS_CTL_370_DATA 0x08000000 +#define DDRSS_CTL_371_DATA 0x06080606 +#define DDRSS_CTL_372_DATA 0x06060806 #define DDRSS_CTL_373_DATA 0x00010101 #define DDRSS_CTL_374_DATA 0x02000000 #define DDRSS_CTL_375_DATA 0x05020101 @@ -407,8 +408,8 @@ #define DDRSS_CTL_389_DATA 0x00000200 #define DDRSS_CTL_390_DATA 0x0000DB60 #define DDRSS_CTL_391_DATA 0x0001E780 -#define DDRSS_CTL_392_DATA 0x0C0D0302 -#define DDRSS_CTL_393_DATA 0x001E090A +#define DDRSS_CTL_392_DATA 0x080D0302 +#define DDRSS_CTL_393_DATA 0x001E0506 #define DDRSS_CTL_394_DATA 0x000030C0 #define DDRSS_CTL_395_DATA 0x00000200 #define DDRSS_CTL_396_DATA 0x00000200 @@ -416,8 +417,8 @@ #define DDRSS_CTL_398_DATA 0x00000200 #define DDRSS_CTL_399_DATA 0x0000DB60 #define DDRSS_CTL_400_DATA 0x0001E780 -#define DDRSS_CTL_401_DATA 0x0C0D0302 -#define DDRSS_CTL_402_DATA 0x001E090A +#define DDRSS_CTL_401_DATA 0x080D0302 +#define DDRSS_CTL_402_DATA 0x001E0506 #define DDRSS_CTL_403_DATA 0x000030C0 #define DDRSS_CTL_404_DATA 0x00000200 #define DDRSS_CTL_405_DATA 0x00000200 @@ -425,8 +426,8 @@ #define DDRSS_CTL_407_DATA 0x00000200 #define DDRSS_CTL_408_DATA 0x0000DB60 #define DDRSS_CTL_409_DATA 0x0001E780 -#define DDRSS_CTL_410_DATA 0x0C0D0302 -#define DDRSS_CTL_411_DATA 0x0000090A +#define DDRSS_CTL_410_DATA 0x080D0302 +#define DDRSS_CTL_411_DATA 0x00000506 #define DDRSS_CTL_412_DATA 0x00000000 #define DDRSS_CTL_413_DATA 0x0302000A #define DDRSS_CTL_414_DATA 0x01000500 @@ -605,14 +606,14 @@ #define DDRSS_PI_164_DATA 0x00007800 #define DDRSS_PI_165_DATA 0x00780078 #define DDRSS_PI_166_DATA 0x00141414 -#define DDRSS_PI_167_DATA 0x0000003A -#define DDRSS_PI_168_DATA 0x0000003A -#define DDRSS_PI_169_DATA 0x0004003A +#define DDRSS_PI_167_DATA 0x00000036 +#define DDRSS_PI_168_DATA 0x00000036 +#define DDRSS_PI_169_DATA 0x00040036 #define DDRSS_PI_170_DATA 0x04000400 -#define DDRSS_PI_171_DATA 0xC8040009 -#define DDRSS_PI_172_DATA 0x0400091C +#define DDRSS_PI_171_DATA 0xC8000009 +#define DDRSS_PI_172_DATA 0x0000091C #define DDRSS_PI_173_DATA 0x00091CC8 -#define DDRSS_PI_174_DATA 0x001CC804 +#define DDRSS_PI_174_DATA 0x001CC800 #define DDRSS_PI_175_DATA 0x00000118 #define DDRSS_PI_176_DATA 0x00001860 #define DDRSS_PI_177_DATA 0x00000118 @@ -622,8 +623,8 @@ #define DDRSS_PI_181_DATA 0x01010404 #define DDRSS_PI_182_DATA 0x00001901 #define DDRSS_PI_183_DATA 0x00190019 -#define DDRSS_PI_184_DATA 0x010C010C -#define DDRSS_PI_185_DATA 0x0000010C +#define DDRSS_PI_184_DATA 0x01080108 +#define DDRSS_PI_185_DATA 0x00000108 #define DDRSS_PI_186_DATA 0x00000000 #define DDRSS_PI_187_DATA 0x05000000 #define DDRSS_PI_188_DATA 0x01010505 @@ -631,9 +632,9 @@ #define DDRSS_PI_190_DATA 0x00181818 #define DDRSS_PI_191_DATA 0x00000000 #define DDRSS_PI_192_DATA 0x00000000 -#define DDRSS_PI_193_DATA 0x0D000000 -#define DDRSS_PI_194_DATA 0x0A0A0D0D -#define DDRSS_PI_195_DATA 0x0303030A +#define DDRSS_PI_193_DATA 0x09000000 +#define DDRSS_PI_194_DATA 0x06060909 +#define DDRSS_PI_195_DATA 0x03030306 #define DDRSS_PI_196_DATA 0x00000000 #define DDRSS_PI_197_DATA 0x00000000 #define DDRSS_PI_198_DATA 0x00000000 @@ -659,32 +660,32 @@ #define DDRSS_PI_218_DATA 0x001600C8 #define DDRSS_PI_219_DATA 0x001600C8 #define DDRSS_PI_220_DATA 0x010100C8 -#define DDRSS_PI_221_DATA 0x00001B01 +#define DDRSS_PI_221_DATA 0x00001701 #define DDRSS_PI_222_DATA 0x1F0F0053 #define DDRSS_PI_223_DATA 0x05000001 -#define DDRSS_PI_224_DATA 0x001B0A0D +#define DDRSS_PI_224_DATA 0x00170A09 #define DDRSS_PI_225_DATA 0x1F0F0053 #define DDRSS_PI_226_DATA 0x05000001 -#define DDRSS_PI_227_DATA 0x001B0A0D +#define DDRSS_PI_227_DATA 0x00170A09 #define DDRSS_PI_228_DATA 0x1F0F0053 #define DDRSS_PI_229_DATA 0x05000001 -#define DDRSS_PI_230_DATA 0x00010A0D +#define DDRSS_PI_230_DATA 0x00010A09 #define DDRSS_PI_231_DATA 0x0C0B0700 #define DDRSS_PI_232_DATA 0x000D0605 #define DDRSS_PI_233_DATA 0x0000C570 #define DDRSS_PI_234_DATA 0x0000001D #define DDRSS_PI_235_DATA 0x180A0800 -#define DDRSS_PI_236_DATA 0x0B071C1C +#define DDRSS_PI_236_DATA 0x0B071818 #define DDRSS_PI_237_DATA 0x0D06050C #define DDRSS_PI_238_DATA 0x0000C570 #define DDRSS_PI_239_DATA 0x0000001D #define DDRSS_PI_240_DATA 0x180A0800 -#define DDRSS_PI_241_DATA 0x0B071C1C +#define DDRSS_PI_241_DATA 0x0B071818 #define DDRSS_PI_242_DATA 0x0D06050C #define DDRSS_PI_243_DATA 0x0000C570 #define DDRSS_PI_244_DATA 0x0000001D #define DDRSS_PI_245_DATA 0x180A0800 -#define DDRSS_PI_246_DATA 0x00001C1C +#define DDRSS_PI_246_DATA 0x00001818 #define DDRSS_PI_247_DATA 0x000030C0 #define DDRSS_PI_248_DATA 0x0001E780 #define DDRSS_PI_249_DATA 0x000030C0 @@ -695,8 +696,8 @@ #define DDRSS_PI_254_DATA 0x03030255 #define DDRSS_PI_255_DATA 0x00025503 #define DDRSS_PI_256_DATA 0x02550255 -#define DDRSS_PI_257_DATA 0x0C080C08 -#define DDRSS_PI_258_DATA 0x00000C08 +#define DDRSS_PI_257_DATA 0x08080808 +#define DDRSS_PI_258_DATA 0x00000808 #define DDRSS_PI_259_DATA 0x000890B8 #define DDRSS_PI_260_DATA 0x00000000 #define DDRSS_PI_261_DATA 0x00000000 @@ -740,7 +741,7 @@ #define DDRSS_PI_299_DATA 0x00000000 #define DDRSS_PI_300_DATA 0x00000000 #define DDRSS_PI_301_DATA 0x00000000 -#define DDRSS_PI_302_DATA 0x00001401 +#define DDRSS_PI_302_DATA 0x00001400 #define DDRSS_PI_303_DATA 0x00000493 #define DDRSS_PI_304_DATA 0x00000000 #define DDRSS_PI_305_DATA 0x00000424 @@ -748,7 +749,7 @@ #define DDRSS_PI_307_DATA 0x00000000 #define DDRSS_PI_308_DATA 0x00000000 #define DDRSS_PI_309_DATA 0x00000000 -#define DDRSS_PI_310_DATA 0x00001401 +#define DDRSS_PI_310_DATA 0x00001400 #define DDRSS_PI_311_DATA 0x00000493 #define DDRSS_PI_312_DATA 0x00000000 #define DDRSS_PI_313_DATA 0x00000424 @@ -756,7 +757,7 @@ #define DDRSS_PI_315_DATA 0x00000000 #define DDRSS_PI_316_DATA 0x00000000 #define DDRSS_PI_317_DATA 0x00000000 -#define DDRSS_PI_318_DATA 0x00001401 +#define DDRSS_PI_318_DATA 0x00001400 #define DDRSS_PI_319_DATA 0x00000493 #define DDRSS_PI_320_DATA 0x00000000 #define DDRSS_PI_321_DATA 0x00000424 @@ -764,7 +765,7 @@ #define DDRSS_PI_323_DATA 0x00000000 #define DDRSS_PI_324_DATA 0x00000000 #define DDRSS_PI_325_DATA 0x00000000 -#define DDRSS_PI_326_DATA 0x00001401 +#define DDRSS_PI_326_DATA 0x00001400 #define DDRSS_PI_327_DATA 0x00000493 #define DDRSS_PI_328_DATA 0x00000000 #define DDRSS_PI_329_DATA 0x00000424 @@ -772,7 +773,7 @@ #define DDRSS_PI_331_DATA 0x00000000 #define DDRSS_PI_332_DATA 0x00000000 #define DDRSS_PI_333_DATA 0x00000000 -#define DDRSS_PI_334_DATA 0x00001401 +#define DDRSS_PI_334_DATA 0x00001400 #define DDRSS_PI_335_DATA 0x00000493 #define DDRSS_PI_336_DATA 0x00000000 #define DDRSS_PI_337_DATA 0x00000424 @@ -780,7 +781,7 @@ #define DDRSS_PI_339_DATA 0x00000000 #define DDRSS_PI_340_DATA 0x00000000 #define DDRSS_PI_341_DATA 0x00000000 -#define DDRSS_PI_342_DATA 0x00001401 +#define DDRSS_PI_342_DATA 0x00001400 #define DDRSS_PI_343_DATA 0x00000493 #define DDRSS_PI_344_DATA 0x00000000 #define DDRSS_PHY_0_DATA 0x04C00000 @@ -2102,7 +2103,7 @@ #define DDRSS_PHY_1316_DATA 0x00000000 #define DDRSS_PHY_1317_DATA 0x00000000 #define DDRSS_PHY_1318_DATA 0x00000000 -#define DDRSS_PHY_1319_DATA 0x07070001 +#define DDRSS_PHY_1319_DATA 0x07030001 #define DDRSS_PHY_1320_DATA 0x00005400 #define DDRSS_PHY_1321_DATA 0x000040A2 #define DDRSS_PHY_1322_DATA 0x00024410 -- 2.34.1
