Update DDR timings to increase stability in higher temperature ranges. Update DDR settings: - SysConfig DDR tool v0.09.05 - Package: ALV - Extended temperature range -40C to 105C - Lower tREFI (ns) to 3900
Signed-off-by: Wadim Egorov <[email protected]> Tested-by: Daniel Schultz <[email protected]> --- .../arm/dts/k3-am64-phycore-som-ddr4-2gb.dtsi | 197 +++++++++--------- 1 file changed, 99 insertions(+), 98 deletions(-) diff --git a/arch/arm/dts/k3-am64-phycore-som-ddr4-2gb.dtsi b/arch/arm/dts/k3-am64-phycore-som-ddr4-2gb.dtsi index 14bccb7f390..9b2e0399610 100644 --- a/arch/arm/dts/k3-am64-phycore-som-ddr4-2gb.dtsi +++ b/arch/arm/dts/k3-am64-phycore-som-ddr4-2gb.dtsi @@ -1,8 +1,8 @@ // SPDX-License-Identifier: GPL-2.0+ /* * This file was generated with the - * AM64x SysConfig DDR Subsystem Register Configuration Tool v0.08.10 - * Wed Dec 15 2021 14:35:01 GMT-0800 (Pacific Standard Time) + * AM64x SysConfig DDR Subsystem Register Configuration Tool v0.09.05 + * Fri Feb 03 2023 11:04:00 GMT+0100 (Mitteleurop??ische Normalzeit) * DDR Type: DDR4 * Frequency = 800MHz (1600MTs) * Density: 16Gb @@ -13,6 +13,7 @@ #define DDRSS_PLL_FREQUENCY_1 400000000 #define DDRSS_PLL_FREQUENCY_2 400000000 + #define DDRSS_CTL_0_DATA 0x00000A00 #define DDRSS_CTL_1_DATA 0x00000000 #define DDRSS_CTL_2_DATA 0x00000000 @@ -58,39 +59,39 @@ #define DDRSS_CTL_42_DATA 0x0400091C #define DDRSS_CTL_43_DATA 0x1C1C1C1C #define DDRSS_CTL_44_DATA 0x05050404 -#define DDRSS_CTL_45_DATA 0x00002806 +#define DDRSS_CTL_45_DATA 0x00002706 #define DDRSS_CTL_46_DATA 0x0602001D -#define DDRSS_CTL_47_DATA 0x05001D0C -#define DDRSS_CTL_48_DATA 0x00280605 +#define DDRSS_CTL_47_DATA 0x05001D0B +#define DDRSS_CTL_48_DATA 0x00270605 #define DDRSS_CTL_49_DATA 0x0602001D -#define DDRSS_CTL_50_DATA 0x05001D0C -#define DDRSS_CTL_51_DATA 0x00280605 +#define DDRSS_CTL_50_DATA 0x05001D0B +#define DDRSS_CTL_51_DATA 0x00270605 #define DDRSS_CTL_52_DATA 0x0602001D -#define DDRSS_CTL_53_DATA 0x07001D0C +#define DDRSS_CTL_53_DATA 0x07001D0B #define DDRSS_CTL_54_DATA 0x00180807 -#define DDRSS_CTL_55_DATA 0x0400DB60 +#define DDRSS_CTL_55_DATA 0x04006DB0 #define DDRSS_CTL_56_DATA 0x07070009 #define DDRSS_CTL_57_DATA 0x00001808 -#define DDRSS_CTL_58_DATA 0x0400DB60 +#define DDRSS_CTL_58_DATA 0x04006DB0 #define DDRSS_CTL_59_DATA 0x07070009 #define DDRSS_CTL_60_DATA 0x00001808 -#define DDRSS_CTL_61_DATA 0x0400DB60 +#define DDRSS_CTL_61_DATA 0x04006DB0 #define DDRSS_CTL_62_DATA 0x03000009 -#define DDRSS_CTL_63_DATA 0x0D0D0002 -#define DDRSS_CTL_64_DATA 0x0D0D0D0D +#define DDRSS_CTL_63_DATA 0x0D0C0002 +#define DDRSS_CTL_64_DATA 0x0D0C0D0C #define DDRSS_CTL_65_DATA 0x01010000 -#define DDRSS_CTL_66_DATA 0x031A1A1A -#define DDRSS_CTL_67_DATA 0x0C0C0C0C -#define DDRSS_CTL_68_DATA 0x00000C0C +#define DDRSS_CTL_66_DATA 0x03191919 +#define DDRSS_CTL_67_DATA 0x0B0B0B0B +#define DDRSS_CTL_68_DATA 0x00000B0B #define DDRSS_CTL_69_DATA 0x00000101 #define DDRSS_CTL_70_DATA 0x00000000 #define DDRSS_CTL_71_DATA 0x01000000 #define DDRSS_CTL_72_DATA 0x01180803 -#define DDRSS_CTL_73_DATA 0x00001860 +#define DDRSS_CTL_73_DATA 0x00000C30 #define DDRSS_CTL_74_DATA 0x00000118 -#define DDRSS_CTL_75_DATA 0x00001860 +#define DDRSS_CTL_75_DATA 0x00000C30 #define DDRSS_CTL_76_DATA 0x00000118 -#define DDRSS_CTL_77_DATA 0x00001860 +#define DDRSS_CTL_77_DATA 0x00000C30 #define DDRSS_CTL_78_DATA 0x00000005 #define DDRSS_CTL_79_DATA 0x00000000 #define DDRSS_CTL_80_DATA 0x00000000 @@ -132,27 +133,27 @@ #define DDRSS_CTL_116_DATA 0x00040003 #define DDRSS_CTL_117_DATA 0x00040005 #define DDRSS_CTL_118_DATA 0x00000000 -#define DDRSS_CTL_119_DATA 0x00061800 -#define DDRSS_CTL_120_DATA 0x00061800 -#define DDRSS_CTL_121_DATA 0x00061800 -#define DDRSS_CTL_122_DATA 0x00061800 -#define DDRSS_CTL_123_DATA 0x00061800 +#define DDRSS_CTL_119_DATA 0x00030C00 +#define DDRSS_CTL_120_DATA 0x00030C00 +#define DDRSS_CTL_121_DATA 0x00030C00 +#define DDRSS_CTL_122_DATA 0x00030C00 +#define DDRSS_CTL_123_DATA 0x00030C00 #define DDRSS_CTL_124_DATA 0x00000000 -#define DDRSS_CTL_125_DATA 0x0000AAA0 -#define DDRSS_CTL_126_DATA 0x00061800 -#define DDRSS_CTL_127_DATA 0x00061800 -#define DDRSS_CTL_128_DATA 0x00061800 -#define DDRSS_CTL_129_DATA 0x00061800 -#define DDRSS_CTL_130_DATA 0x00061800 +#define DDRSS_CTL_125_DATA 0x00005550 +#define DDRSS_CTL_126_DATA 0x00030C00 +#define DDRSS_CTL_127_DATA 0x00030C00 +#define DDRSS_CTL_128_DATA 0x00030C00 +#define DDRSS_CTL_129_DATA 0x00030C00 +#define DDRSS_CTL_130_DATA 0x00030C00 #define DDRSS_CTL_131_DATA 0x00000000 -#define DDRSS_CTL_132_DATA 0x0000AAA0 -#define DDRSS_CTL_133_DATA 0x00061800 -#define DDRSS_CTL_134_DATA 0x00061800 -#define DDRSS_CTL_135_DATA 0x00061800 -#define DDRSS_CTL_136_DATA 0x00061800 -#define DDRSS_CTL_137_DATA 0x00061800 +#define DDRSS_CTL_132_DATA 0x00005550 +#define DDRSS_CTL_133_DATA 0x00030C00 +#define DDRSS_CTL_134_DATA 0x00030C00 +#define DDRSS_CTL_135_DATA 0x00030C00 +#define DDRSS_CTL_136_DATA 0x00030C00 +#define DDRSS_CTL_137_DATA 0x00030C00 #define DDRSS_CTL_138_DATA 0x00000000 -#define DDRSS_CTL_139_DATA 0x0000AAA0 +#define DDRSS_CTL_139_DATA 0x00005550 #define DDRSS_CTL_140_DATA 0x00000000 #define DDRSS_CTL_141_DATA 0x00000000 #define DDRSS_CTL_142_DATA 0x00000000 @@ -178,7 +179,7 @@ #define DDRSS_CTL_162_DATA 0x0E0A0907 #define DDRSS_CTL_163_DATA 0x0A090000 #define DDRSS_CTL_164_DATA 0x0A090701 -#define DDRSS_CTL_165_DATA 0x0000000E +#define DDRSS_CTL_165_DATA 0x0000080E #define DDRSS_CTL_166_DATA 0x00040003 #define DDRSS_CTL_167_DATA 0x00000007 #define DDRSS_CTL_168_DATA 0x00000000 @@ -219,22 +220,22 @@ #define DDRSS_CTL_203_DATA 0x00000000 #define DDRSS_CTL_204_DATA 0x00042400 #define DDRSS_CTL_205_DATA 0x00000301 -#define DDRSS_CTL_206_DATA 0x00000000 +#define DDRSS_CTL_206_DATA 0x000000C0 #define DDRSS_CTL_207_DATA 0x00000424 #define DDRSS_CTL_208_DATA 0x00000301 -#define DDRSS_CTL_209_DATA 0x00000000 +#define DDRSS_CTL_209_DATA 0x000000C0 #define DDRSS_CTL_210_DATA 0x00000424 #define DDRSS_CTL_211_DATA 0x00000301 -#define DDRSS_CTL_212_DATA 0x00000000 +#define DDRSS_CTL_212_DATA 0x000000C0 #define DDRSS_CTL_213_DATA 0x00000424 #define DDRSS_CTL_214_DATA 0x00000301 -#define DDRSS_CTL_215_DATA 0x00000000 +#define DDRSS_CTL_215_DATA 0x000000C0 #define DDRSS_CTL_216_DATA 0x00000424 #define DDRSS_CTL_217_DATA 0x00000301 -#define DDRSS_CTL_218_DATA 0x00000000 +#define DDRSS_CTL_218_DATA 0x000000C0 #define DDRSS_CTL_219_DATA 0x00000424 #define DDRSS_CTL_220_DATA 0x00000301 -#define DDRSS_CTL_221_DATA 0x00000000 +#define DDRSS_CTL_221_DATA 0x000000C0 #define DDRSS_CTL_222_DATA 0x00000000 #define DDRSS_CTL_223_DATA 0x00000000 #define DDRSS_CTL_224_DATA 0x00000000 @@ -243,12 +244,12 @@ #define DDRSS_CTL_227_DATA 0x00000000 #define DDRSS_CTL_228_DATA 0x00000000 #define DDRSS_CTL_229_DATA 0x00000000 -#define DDRSS_CTL_230_DATA 0x00000000 -#define DDRSS_CTL_231_DATA 0x00000000 -#define DDRSS_CTL_232_DATA 0x00000000 -#define DDRSS_CTL_233_DATA 0x00000000 -#define DDRSS_CTL_234_DATA 0x00000000 -#define DDRSS_CTL_235_DATA 0x00000000 +#define DDRSS_CTL_230_DATA 0x0000000C +#define DDRSS_CTL_231_DATA 0x0000000C +#define DDRSS_CTL_232_DATA 0x0000000C +#define DDRSS_CTL_233_DATA 0x0000000C +#define DDRSS_CTL_234_DATA 0x0000000C +#define DDRSS_CTL_235_DATA 0x0000000C #define DDRSS_CTL_236_DATA 0x00001401 #define DDRSS_CTL_237_DATA 0x00001401 #define DDRSS_CTL_238_DATA 0x00001401 @@ -334,7 +335,7 @@ #define DDRSS_CTL_318_DATA 0x3FFF0000 #define DDRSS_CTL_319_DATA 0x000FFF00 #define DDRSS_CTL_320_DATA 0xFFFFFFFF -#define DDRSS_CTL_321_DATA 0x000FFF00 +#define DDRSS_CTL_321_DATA 0x00FFFF00 #define DDRSS_CTL_322_DATA 0x0A000000 #define DDRSS_CTL_323_DATA 0x0001FFFF #define DDRSS_CTL_324_DATA 0x01010101 @@ -343,7 +344,7 @@ #define DDRSS_CTL_327_DATA 0x00000C01 #define DDRSS_CTL_328_DATA 0x00000000 #define DDRSS_CTL_329_DATA 0x00000000 -#define DDRSS_CTL_330_DATA 0x01000000 +#define DDRSS_CTL_330_DATA 0x00000000 #define DDRSS_CTL_331_DATA 0x01000000 #define DDRSS_CTL_332_DATA 0x00000100 #define DDRSS_CTL_333_DATA 0x00010000 @@ -398,31 +399,31 @@ #define DDRSS_CTL_382_DATA 0x00000000 #define DDRSS_CTL_383_DATA 0x04000100 #define DDRSS_CTL_384_DATA 0x1E000004 -#define DDRSS_CTL_385_DATA 0x000030C0 +#define DDRSS_CTL_385_DATA 0x00001860 #define DDRSS_CTL_386_DATA 0x00000200 #define DDRSS_CTL_387_DATA 0x00000200 #define DDRSS_CTL_388_DATA 0x00000200 #define DDRSS_CTL_389_DATA 0x00000200 -#define DDRSS_CTL_390_DATA 0x0000DB60 -#define DDRSS_CTL_391_DATA 0x0001E780 +#define DDRSS_CTL_390_DATA 0x00006DB0 +#define DDRSS_CTL_391_DATA 0x0000F3C0 #define DDRSS_CTL_392_DATA 0x0C0D0302 #define DDRSS_CTL_393_DATA 0x001E090A -#define DDRSS_CTL_394_DATA 0x000030C0 +#define DDRSS_CTL_394_DATA 0x00001860 #define DDRSS_CTL_395_DATA 0x00000200 #define DDRSS_CTL_396_DATA 0x00000200 #define DDRSS_CTL_397_DATA 0x00000200 #define DDRSS_CTL_398_DATA 0x00000200 -#define DDRSS_CTL_399_DATA 0x0000DB60 -#define DDRSS_CTL_400_DATA 0x0001E780 +#define DDRSS_CTL_399_DATA 0x00006DB0 +#define DDRSS_CTL_400_DATA 0x0000F3C0 #define DDRSS_CTL_401_DATA 0x0C0D0302 #define DDRSS_CTL_402_DATA 0x001E090A -#define DDRSS_CTL_403_DATA 0x000030C0 +#define DDRSS_CTL_403_DATA 0x00001860 #define DDRSS_CTL_404_DATA 0x00000200 #define DDRSS_CTL_405_DATA 0x00000200 #define DDRSS_CTL_406_DATA 0x00000200 #define DDRSS_CTL_407_DATA 0x00000200 -#define DDRSS_CTL_408_DATA 0x0000DB60 -#define DDRSS_CTL_409_DATA 0x0001E780 +#define DDRSS_CTL_408_DATA 0x00006DB0 +#define DDRSS_CTL_409_DATA 0x0000F3C0 #define DDRSS_CTL_410_DATA 0x0C0D0302 #define DDRSS_CTL_411_DATA 0x0000090A #define DDRSS_CTL_412_DATA 0x00000000 @@ -607,16 +608,16 @@ #define DDRSS_PI_168_DATA 0x0000003A #define DDRSS_PI_169_DATA 0x0004003A #define DDRSS_PI_170_DATA 0x04000400 -#define DDRSS_PI_171_DATA 0x68040009 +#define DDRSS_PI_171_DATA 0xC8040009 #define DDRSS_PI_172_DATA 0x0400091C -#define DDRSS_PI_173_DATA 0x00091C68 -#define DDRSS_PI_174_DATA 0x001C6804 +#define DDRSS_PI_173_DATA 0x00091CC8 +#define DDRSS_PI_174_DATA 0x001CC804 #define DDRSS_PI_175_DATA 0x00000118 -#define DDRSS_PI_176_DATA 0x00001860 +#define DDRSS_PI_176_DATA 0x00000C30 #define DDRSS_PI_177_DATA 0x00000118 -#define DDRSS_PI_178_DATA 0x00001860 +#define DDRSS_PI_178_DATA 0x00000C30 #define DDRSS_PI_179_DATA 0x00000118 -#define DDRSS_PI_180_DATA 0x04001860 +#define DDRSS_PI_180_DATA 0x04000C30 #define DDRSS_PI_181_DATA 0x01010404 #define DDRSS_PI_182_DATA 0x00001901 #define DDRSS_PI_183_DATA 0x00190019 @@ -667,28 +668,28 @@ #define DDRSS_PI_228_DATA 0x1F0F0053 #define DDRSS_PI_229_DATA 0x05000001 #define DDRSS_PI_230_DATA 0x00010A0D -#define DDRSS_PI_231_DATA 0x0D0C0700 +#define DDRSS_PI_231_DATA 0x0C0B0700 #define DDRSS_PI_232_DATA 0x000D0605 -#define DDRSS_PI_233_DATA 0x0000C570 +#define DDRSS_PI_233_DATA 0x000062B8 #define DDRSS_PI_234_DATA 0x0000001D #define DDRSS_PI_235_DATA 0x180A0800 -#define DDRSS_PI_236_DATA 0x0C071C1C -#define DDRSS_PI_237_DATA 0x0D06050D -#define DDRSS_PI_238_DATA 0x0000C570 +#define DDRSS_PI_236_DATA 0x0B071C1C +#define DDRSS_PI_237_DATA 0x0D06050C +#define DDRSS_PI_238_DATA 0x000062B8 #define DDRSS_PI_239_DATA 0x0000001D #define DDRSS_PI_240_DATA 0x180A0800 -#define DDRSS_PI_241_DATA 0x0C071C1C -#define DDRSS_PI_242_DATA 0x0D06050D -#define DDRSS_PI_243_DATA 0x0000C570 +#define DDRSS_PI_241_DATA 0x0B071C1C +#define DDRSS_PI_242_DATA 0x0D06050C +#define DDRSS_PI_243_DATA 0x000062B8 #define DDRSS_PI_244_DATA 0x0000001D #define DDRSS_PI_245_DATA 0x180A0800 #define DDRSS_PI_246_DATA 0x00001C1C -#define DDRSS_PI_247_DATA 0x000030C0 -#define DDRSS_PI_248_DATA 0x0001E780 -#define DDRSS_PI_249_DATA 0x000030C0 -#define DDRSS_PI_250_DATA 0x0001E780 -#define DDRSS_PI_251_DATA 0x000030C0 -#define DDRSS_PI_252_DATA 0x0001E780 +#define DDRSS_PI_247_DATA 0x00001860 +#define DDRSS_PI_248_DATA 0x0000F3C0 +#define DDRSS_PI_249_DATA 0x00001860 +#define DDRSS_PI_250_DATA 0x0000F3C0 +#define DDRSS_PI_251_DATA 0x00001860 +#define DDRSS_PI_252_DATA 0x0000F3C0 #define DDRSS_PI_253_DATA 0x02550255 #define DDRSS_PI_254_DATA 0x03030255 #define DDRSS_PI_255_DATA 0x00025503 @@ -735,49 +736,49 @@ #define DDRSS_PI_296_DATA 0x00000000 #define DDRSS_PI_297_DATA 0x00000424 #define DDRSS_PI_298_DATA 0x00000301 -#define DDRSS_PI_299_DATA 0x00000000 +#define DDRSS_PI_299_DATA 0x000000C0 #define DDRSS_PI_300_DATA 0x00000000 -#define DDRSS_PI_301_DATA 0x00000000 +#define DDRSS_PI_301_DATA 0x0000000C #define DDRSS_PI_302_DATA 0x00001401 #define DDRSS_PI_303_DATA 0x00000493 #define DDRSS_PI_304_DATA 0x00000000 #define DDRSS_PI_305_DATA 0x00000424 #define DDRSS_PI_306_DATA 0x00000301 -#define DDRSS_PI_307_DATA 0x00000000 +#define DDRSS_PI_307_DATA 0x000000C0 #define DDRSS_PI_308_DATA 0x00000000 -#define DDRSS_PI_309_DATA 0x00000000 +#define DDRSS_PI_309_DATA 0x0000000C #define DDRSS_PI_310_DATA 0x00001401 #define DDRSS_PI_311_DATA 0x00000493 #define DDRSS_PI_312_DATA 0x00000000 #define DDRSS_PI_313_DATA 0x00000424 #define DDRSS_PI_314_DATA 0x00000301 -#define DDRSS_PI_315_DATA 0x00000000 +#define DDRSS_PI_315_DATA 0x000000C0 #define DDRSS_PI_316_DATA 0x00000000 -#define DDRSS_PI_317_DATA 0x00000000 +#define DDRSS_PI_317_DATA 0x0000000C #define DDRSS_PI_318_DATA 0x00001401 #define DDRSS_PI_319_DATA 0x00000493 #define DDRSS_PI_320_DATA 0x00000000 #define DDRSS_PI_321_DATA 0x00000424 #define DDRSS_PI_322_DATA 0x00000301 -#define DDRSS_PI_323_DATA 0x00000000 +#define DDRSS_PI_323_DATA 0x000000C0 #define DDRSS_PI_324_DATA 0x00000000 -#define DDRSS_PI_325_DATA 0x00000000 +#define DDRSS_PI_325_DATA 0x0000000C #define DDRSS_PI_326_DATA 0x00001401 #define DDRSS_PI_327_DATA 0x00000493 #define DDRSS_PI_328_DATA 0x00000000 #define DDRSS_PI_329_DATA 0x00000424 #define DDRSS_PI_330_DATA 0x00000301 -#define DDRSS_PI_331_DATA 0x00000000 +#define DDRSS_PI_331_DATA 0x000000C0 #define DDRSS_PI_332_DATA 0x00000000 -#define DDRSS_PI_333_DATA 0x00000000 +#define DDRSS_PI_333_DATA 0x0000000C #define DDRSS_PI_334_DATA 0x00001401 #define DDRSS_PI_335_DATA 0x00000493 #define DDRSS_PI_336_DATA 0x00000000 #define DDRSS_PI_337_DATA 0x00000424 #define DDRSS_PI_338_DATA 0x00000301 -#define DDRSS_PI_339_DATA 0x00000000 +#define DDRSS_PI_339_DATA 0x000000C0 #define DDRSS_PI_340_DATA 0x00000000 -#define DDRSS_PI_341_DATA 0x00000000 +#define DDRSS_PI_341_DATA 0x0000000C #define DDRSS_PI_342_DATA 0x00001401 #define DDRSS_PI_343_DATA 0x00000493 #define DDRSS_PI_344_DATA 0x00000000 @@ -901,7 +902,7 @@ #define DDRSS_PHY_117_DATA 0x00800080 #define DDRSS_PHY_118_DATA 0x00800080 #define DDRSS_PHY_119_DATA 0x01000080 -#define DDRSS_PHY_120_DATA 0x01A00000 +#define DDRSS_PHY_120_DATA 0x01000000 #define DDRSS_PHY_121_DATA 0x00000000 #define DDRSS_PHY_122_DATA 0x00000000 #define DDRSS_PHY_123_DATA 0x00080200 @@ -1157,7 +1158,7 @@ #define DDRSS_PHY_373_DATA 0x00800080 #define DDRSS_PHY_374_DATA 0x00800080 #define DDRSS_PHY_375_DATA 0x01000080 -#define DDRSS_PHY_376_DATA 0x01A00000 +#define DDRSS_PHY_376_DATA 0x01000000 #define DDRSS_PHY_377_DATA 0x00000000 #define DDRSS_PHY_378_DATA 0x00000000 #define DDRSS_PHY_379_DATA 0x00080200 @@ -2115,7 +2116,7 @@ #define DDRSS_PHY_1331_DATA 0x00004410 #define DDRSS_PHY_1332_DATA 0x00000000 #define DDRSS_PHY_1333_DATA 0x00000046 -#define DDRSS_PHY_1334_DATA 0x00010000 +#define DDRSS_PHY_1334_DATA 0x00000400 #define DDRSS_PHY_1335_DATA 0x00000008 #define DDRSS_PHY_1336_DATA 0x00000000 #define DDRSS_PHY_1337_DATA 0x00000000 @@ -2152,7 +2153,7 @@ #define DDRSS_PHY_1368_DATA 0x00000002 #define DDRSS_PHY_1369_DATA 0x00000100 #define DDRSS_PHY_1370_DATA 0x00000000 -#define DDRSS_PHY_1371_DATA 0x0001F7C0 +#define DDRSS_PHY_1371_DATA 0x00000FC3 #define DDRSS_PHY_1372_DATA 0x00020002 #define DDRSS_PHY_1373_DATA 0x00000000 #define DDRSS_PHY_1374_DATA 0x00001142 @@ -2186,4 +2187,4 @@ #define DDRSS_PHY_1402_DATA 0x01990000 #define DDRSS_PHY_1403_DATA 0x300D3F11 #define DDRSS_PHY_1404_DATA 0x01990000 -#define DDRSS_PHY_1405_DATA 0x20040001 +#define DDRSS_PHY_1405_DATA 0x20040004 -- 2.48.1
