Hi Andre, On 01:40 Fri 02 Jan , Andre Przywara wrote: > On Sun, 30 Nov 2025 21:45:11 +0000 > Yixun Lan <[email protected]> wrote: > > > Add some ciritial SPL settings for A733 SoC > > > > - Set SPL MAX SIZE to 180KB, 0x47000 - 0x74000 > > - Set SPL running address to 0x47000, with a header padded before > > the image, so the final SPL text address need to shift 0x60 bytes. > > - Set Stack address > > The patch separation for those addresses looks a bit arbitrary, since > there are other SPL specific addresses in patch 01/10, and we don't > really support an SPL anyway. strictly, we still need SPL stage, for cpu to fully switching to 64bit mode, as the initial brom/boot0 are running in 32bit, also currently I rely on SPL to chainload u-boot image with CONFIG_SPL_RAM_DEVICE support.
and yes, the only missing part is DDR initialzation in SPL.. > So either drop this patch, or merge it into the previous one. > I will merge them into previous patch, thanks > Cheers, > Andre > -- Yixun Lan (dlan)
