> -----Original Message-----
> From: Ng, Boon Khai <[email protected]>
> Sent: Thursday, August 14, 2025 11:18 AM
> To: U-boot Openlist <[email protected]>
> Cc: Tom Rini <[email protected]>; Simon Glass <[email protected]>;
> Marek Vasut <[email protected]>; Simon Goldschmidt
> <[email protected]>; Chee, Tien Fong
> <[email protected]>; Maniyam, Dinesh
> <[email protected]>; Yuslaimi, Alif Zakuan
> <[email protected]>; Lim, Jit Loon <[email protected]>;
> Ng, Boon Khai <[email protected]>; Kathpalia, Tanmay
> <[email protected]>; Ilias Apalodimas
> <[email protected]>; Jerome Forissier
> <[email protected]>; Rao, Mahesh <[email protected]>
> Subject: [PATCH v2 3/3] configs: agilex5: Enable config SPL_SYS_DCACHE_OFF
>
> Add SPL_SYS_DCACHE_OFF to Agilex5 defconfig to disable data cache for SPL
>
> Signed-off-by: Tanmay Kathpalia <[email protected]>
> Signed-off-by: Boon Khai Ng <[email protected]>
> ---
> configs/socfpga_agilex5_defconfig | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/configs/socfpga_agilex5_defconfig
> b/configs/socfpga_agilex5_defconfig
> index 33a6221979a..8c31dcfea11 100644
> --- a/configs/socfpga_agilex5_defconfig
> +++ b/configs/socfpga_agilex5_defconfig
> @@ -45,6 +45,7 @@ CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
> CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0xbfa00000
> CONFIG_SPL_SYS_MALLOC_SIZE=0x500000
> CONFIG_SPL_CACHE=y
> +CONFIG_SPL_SYS_DCACHE_OFF=y
> CONFIG_SPL_MTD=y
> CONFIG_SPL_SPI_FLASH_MTD=y
> CONFIG_SPL_SPI_LOAD=y
> --
> 2.35.3
Reviewed-by: Tien Fong Chee <[email protected]>
Best regards,
Tien Fong
