From: Tingting Meng <[email protected]> Agilex7 M-series support has been added using upstream Linux DTS.
socfpga_agilex_socdk-u-boot.dtsi was updated to support both Agilex and Agilex7 M-series platforms. Signed-off-by: Tingting Meng <[email protected]> Signed-off-by: Alif Zakuan Yuslaimi <[email protected]> --- arch/arm/dts/socfpga_agilex-u-boot.dtsi | 7 ++ arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi | 92 ++++++++++++++++++- board/intel/agilex7m-socdk/MAINTAINERS | 9 ++ 3 files changed, 107 insertions(+), 1 deletion(-) create mode 100644 board/intel/agilex7m-socdk/MAINTAINERS diff --git a/arch/arm/dts/socfpga_agilex-u-boot.dtsi b/arch/arm/dts/socfpga_agilex-u-boot.dtsi index 8c9bdf610ae..770f6cad292 100644 --- a/arch/arm/dts/socfpga_agilex-u-boot.dtsi +++ b/arch/arm/dts/socfpga_agilex-u-boot.dtsi @@ -263,3 +263,10 @@ /delete-node/ kernel; }; #endif + +#ifdef CONFIG_TARGET_SOCFPGA_AGILEX7M +&sdr { + compatible = "intel,sdr-ctl-agilex7m"; + reg = <0xf8020000 0x100>; +}; +#endif diff --git a/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi index 369d9585174..6f2fe7bf746 100644 --- a/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi +++ b/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi @@ -8,6 +8,7 @@ #include "socfpga_agilex-u-boot.dtsi" +#ifdef CONFIG_TARGET_SOCFPGA_AGILEX /{ chosen { stdout-path = "serial0:115200n8"; @@ -21,6 +22,96 @@ }; }; +&qspi { + status = "okay"; +}; +#endif + +#ifdef CONFIG_TARGET_SOCFPGA_AGILEX7M +/{ + model = "SoCFPGA Agilex7-M SoCDK"; + chosen { + stdout-path = "serial0:115200n8"; + u-boot,spl-boot-order = &mmc; + }; + + memory@0 { + /* + * When LPDDR ECC is enabled, the last 1/8 of the memory region must + * be reserved for the Inline ECC buffer. + * + * Example for memory size with 2GB: + * memory { + * reg = <0x0 0x00000000 0x0 0x80000000>; + * }; + * + * Example for memory size with 8GB: + * memory { + * reg = <0x0 0x00000000 0x0 0x80000000>, + * <0x1 0x00000000 0x1 0x80000000>; + * }; + * + * + * Example for memory size with 2GB with LPDDR Inline ECC ON: + * memory { + * reg = <0x0 0x00000000 0x0 0x70000000>; + * }; + * + * Example for memory size with 8GB with LPDDR Inline ECC ON: + * memory { + * reg = <0x0 0x00000000 0x0 0x80000000>, + * <0x1 0x00000000 0x1 0x40000000>; + * }; + */ + + /* Default memory size is 2GB */ + reg = <0x0 0x00000000 0x0 0x80000000>; + }; +}; + +&gmac2 { + status = "okay"; + phy-mode = "rgmii"; + phy-handle = <&phy0>; + + max-frame-size = <3800>; + + mdio2 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + phy2: ethernet-phy@2 { + reg = <4>; + + txd0-skew-ps = <0>; /* -420ps */ + txd1-skew-ps = <0>; /* -420ps */ + txd2-skew-ps = <0>; /* -420ps */ + txd3-skew-ps = <0>; /* -420ps */ + rxd0-skew-ps = <420>; /* 0ps */ + rxd1-skew-ps = <420>; /* 0ps */ + rxd2-skew-ps = <420>; /* 0ps */ + rxd3-skew-ps = <420>; /* 0ps */ + txen-skew-ps = <0>; /* -420ps */ + txc-skew-ps = <1860>; /* 960ps */ + rxdv-skew-ps = <420>; /* 0ps */ + rxc-skew-ps = <1680>; /* 780ps */ + }; + }; +}; + +&qspi { + status = "disabled"; +}; + +&socfpga_l3interconnect_firewall { + soc_noc_fw_mpfe_csr_inst_0_mpfe_scr@f8020000 { + intel,offset-settings = + /* Disable MPFE firewall for SMMU */ + <0x00000000 0x00010101 0x00010101>; + }; +}; +#endif + &gmac0 { mdio0 { ethernet_phy0: ethernet-phy@0 { @@ -54,7 +145,6 @@ }; &qspi { - status = "okay"; /delete-property/ clocks; }; diff --git a/board/intel/agilex7m-socdk/MAINTAINERS b/board/intel/agilex7m-socdk/MAINTAINERS new file mode 100644 index 00000000000..d69e614a0be --- /dev/null +++ b/board/intel/agilex7m-socdk/MAINTAINERS @@ -0,0 +1,9 @@ +SOCFPGA BOARD +M: Tien Fong Chee <[email protected]> +M: Alif Zakuan Yuslaimi <[email protected]> +S: Maintained +F: arch/arm/dts/socfpga_soc64_u-boot.dtsi +F: arch/arm/dts/socfpga_agilex7m* +F: board/intel/agilex7m-socdk/ +F: include/configs/socfpga_agilex7m_socdk.h +F: configs/socfpga_agilex7m_sdmmc_defconfig -- 2.35.3
