On 7/30/25 14:53, Patrice Chotard wrote:
> STM32F4/F7 and H7 series doesn't have a clear reset register, so
> set_clr field must be set to false.
>
> Fixes: 0994a627c278 ("reset: stm32mp25: add stm32mp25 reset driver")
>
> Signed-off-by: Patrice Chotard <[email protected]>
> ---
>
> drivers/reset/stm32/stm32-reset.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/reset/stm32/stm32-reset.c
> b/drivers/reset/stm32/stm32-reset.c
> index 918e81e588f..024f15cb25e 100644
> --- a/drivers/reset/stm32/stm32-reset.c
> +++ b/drivers/reset/stm32/stm32-reset.c
> @@ -19,7 +19,7 @@ static const struct stm32_reset_cfg
> *stm32_get_reset_line(struct reset_ctl *rese
>
> ptr_line->offset = bank;
> ptr_line->bit_idx = offset;
> - ptr_line->set_clr = true;
> + ptr_line->set_clr = false;
>
> return ptr_line;
> }
Applied to u-boot-stm32/master
Thanks
Patrice
