On 7/30/25 19:23, Tom Rini wrote:
On Wed, Jul 30, 2025 at 01:25:09PM +0200, Michal Simek wrote:

After upgrading to QEMU 10 by commit 1d782a3f229c ("Docker, CI: Update to
latest Ubuntu and Dockerfile") let's wire mbv32 which is the part of QEMU
to have it under regression.

Signed-off-by: Michal Simek <[email protected]>
---

gitlab I have tested.
azure I didn't test it but did blindly all changes as they are in github
one.

This patch has be applied on the top of this series
https://lore.kernel.org/r/[email protected]

For v2, take this via your tree.

[snip]
---
  .azure-pipelines.yml | 20 ++++++++++++++++++--
  .gitlab-ci.yml       | 32 ++++++++++++++++++++++++++++++--
  2 files changed, 48 insertions(+), 4 deletions(-)

diff --git a/.azure-pipelines.yml b/.azure-pipelines.yml
index 8209d2b329cb..76a0ba097f93 100644
--- a/.azure-pipelines.yml
+++ b/.azure-pipelines.yml
@@ -258,11 +258,11 @@ stages:
            ln -s u_boot_boardenv_qemu_arm64_na.py 
/tmp/uboot-test-hooks/py/travis-ci/u_boot_boardenv_qemu_arm64_lwip_na.py
            ln -s travis-ci /tmp/uboot-test-hooks/bin/\`hostname\`
            ln -s travis-ci /tmp/uboot-test-hooks/py/\`hostname\`
-          if [[ "\${TEST_PY_BD}" == "qemu-riscv32_spl" ]]; then
+          if [[ "\${TEST_PY_BD}" == "qemu-riscv32_spl" ]] || [[ "${TEST_PY_BD}" == 
"xilinx_mbv32_smode" ]]; then

You missed an escape here and it should be:
"\${TEST_PY_BD}" == "xilinx_mbv32_smode"

                wget -O - 
https://github.com/riscv-software-src/opensbi/releases/download/v1.3.1/opensbi-1.3.1-rv-bin.tar.xz
 | tar -C /tmp -xJ;
                export 
OPENSBI=/tmp/opensbi-1.3.1-rv-bin/share/opensbi/ilp32/generic/firmware/fw_dynamic.bin;
            fi
-          if [[ "\${TEST_PY_BD}" == "qemu-riscv64_spl" ]] || [[ "\${TEST_PY_BD}" == 
"sifive_unleashed" ]]; then
+          if [[ "\${TEST_PY_BD}" == "qemu-riscv64_spl" ]] || [[ "\${TEST_PY_BD}" == 
"sifive_unleashed" ]] || [[ "${TEST_PY_BD}" == "xilinx_mbv64_smode" ]]; then

Same here.

The rest of the Azure side looks right.


Sent v2 with this fixed and yes will take it via my tree.

Thanks,
Michal

--
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Xilinx Microblaze
Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP/Versal ARM64 SoCs
U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal/Versal NET SoCs
TF-A maintainer - Xilinx ZynqMP/Versal/Versal NET SoCs

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