Hi, On 7/1/2025 3:53 PM, Francesco Valla wrote: [...]
> > that was exactly the issue, after unlocking the CTRL_MMR region the > TB_CLKEN bits wrote correctly and the PWM started working again. > According to TRM, the correct region is number 1. > Ah yes, sorry for the confusion > These were the issued commands to unlock the CTRL_MMR region 1: > > $ devmem2 0x105008 w 0x68EF3490 > $ devmem2 0x10500C w 0xD172BC5A > > and then to write TB_CLKEN for PWM channel 0: > > $ devmem2 0x00104130 w 0x1 > > The clock then is marked as enabled also from a hardware point of view: > > $ head -n 2 /sys/kernel/debug/clk/clk_summary && cat /sys/kernel/debug/ > clk/clk_summary | grep pwm > > enable prepare protect > duty hardware connection > clock count count count rate > accuracy phase cycle enable consumer id > epwm_tbclk2 0 0 0 0 > 0 0 50000 Y deviceless > no_connection_id > epwm_tbclk1 0 0 0 0 > 0 0 50000 N deviceless > no_connection_id > epwm_tbclk0 1 1 0 0 > 0 0 50000 N 23000000.pwm tbclk > clk:86:0 0 0 0 250000000 > 0 0 50000 Y 23000000.pwm fck > > > What's the correct path to issue a bug for the DM firmware? > Thanks for the confirmation. I am tracking this internally with firmware team. Will let you know once the fix is available. > Thank you! > > Regards, > Francesco
