On June 13, 2025 thus sayeth Markus Schneider-Pargmann:
> In IO+DDR the DDR is kept in self-refresh while the SoC cores are
> powered off completely. During boot the normal initialization routine of
> DDR is slightly different to exit self-refresh and keep the DDR contents.
>
> Signed-off-by: Markus Schneider-Pargmann <[email protected]>
> ---
> drivers/ram/k3-ddrss/k3-ddrss.c | 165
> ++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 165 insertions(+)
>
> diff --git a/drivers/ram/k3-ddrss/k3-ddrss.c b/drivers/ram/k3-ddrss/k3-ddrss.c
> index
> ff87faf6a22419e54d3639817ad2b884a97a3911..d7ae6e9ef24d5aebdb61656e6ca797b1799ca0f6
> 100644
> --- a/drivers/ram/k3-ddrss/k3-ddrss.c
> +++ b/drivers/ram/k3-ddrss/k3-ddrss.c
...
> +
> +static void k3_ddrss_lpm_resume(struct k3_ddrss_desc *ddrss)
> +{
> + k3_ddrss_reg_update_bits(ddrss->ddrss_ctl_cfg,
> + K3_DDRSS_CFG_DENALI_CTL_160,
> + K3_DDRSS_CFG_DENALI_CTL_160_LP_CMD_MASK,
> + K3_DDRSS_CFG_DENALI_CTL_160_LP_CMD_ENTRY);
> + while (!(readl(ddrss->ddrss_ctl_cfg + K3_DDRSS_CFG_DENALI_CTL_345) &
> + (1 << K3_DDRSS_CFG_DENALI_CTL_345_INT_STATUS_LOWPOWER_SHIFT)))
> + ;
Can we use the wait_for_bit_* logic here?
> +
> + k3_ddrss_reg_update_bits(ddrss->ddrss_ctl_cfg,
> + K3_DDRSS_CFG_DENALI_CTL_353,
> + 0,
> + 1 <<
> K3_DDRSS_CFG_DENALI_CTL_353_INT_ACK_LOWPOWER_SHIFT);
> + while ((readl(ddrss->ddrss_ctl_cfg + K3_DDRSS_CFG_DENALI_CTL_169) &
> + K3_DDRSS_CFG_DENALI_CTL_169_LP_STATE_MASK) !=
> + 0x40 << K3_DDRSS_CFG_DENALI_CTL_169_LP_STATE_SHIFT)
> + ;
I know DRAM is so early on in the bringup that we'll probably have a
debugger nearby already but just having an error message to grep for
could really help if the controller never acknowledges this.
~Bryan
