Hi Tom, The following changes since commit e96b6c0c18c29fba63a1ceb21dc29afb9d9b2910:
Merge patch series "Remove as much arch/arm/dts/*.h as possible" (2025-06-06 13:54:42 -0600) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-riscv.git next for you to fetch changes up to c89f2b10784f940ce8e177348efff5538e905b5f: MAINTAINERS: riscv: cpu: th1520: Assign myself as maintainer (2025-06-09 10:44:14 +0800) CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/26569 ---------------------------------------------------------------- - SoC: add SPL support for licheepi4a - RISC-V: raise SPL_SYS_MALLOC_SIZE to 8 MiB ---------------------------------------------------------------- Heinrich Schuchardt (1): configs: raise SPL_SYS_MALLOC_SIZE to 8 MiB on RISC-V Yao Zi (6): riscv: cpu: th1520: Build spl.c for SPL only riscv: cpu: th1520: Support cache enabling/disabling in M mode only riscv: dts: th1520: Prepare binman configuration for loading OpenSBI board: thead: licheepi4a: Run proper U-Boot in S-Mode doc: thead: lpi4a: Update for S-Mode proper U-Boot support MAINTAINERS: riscv: cpu: th1520: Assign myself as maintainer MAINTAINERS | 7 ++ arch/riscv/cpu/th1520/Makefile | 2 +- arch/riscv/cpu/th1520/cache.c | 2 + arch/riscv/dts/thead-th1520-binman.dtsi | 32 +++++++- common/spl/Kconfig | 2 +- configs/starfive_visionfive2_defconfig | 1 - configs/th1520_lpi4a_defconfig | 2 +- configs/xilinx_mbv32_defconfig | 1 - configs/xilinx_mbv32_smode_defconfig | 1 - configs/xilinx_mbv64_defconfig | 1 - configs/xilinx_mbv64_smode_defconfig | 1 - doc/board/thead/lpi4a.rst | 125 +++++++++----------------------- 12 files changed, 76 insertions(+), 101 deletions(-) Best regards, Leo
