Alias name for freeze_controller is corrected in all Altera SoC FPGA dts files. The '_' character is corrected to '-' as per device tree schema standard.
Signed-off-by: Naresh Kumar Ravulapalli <[email protected]> --- arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi | 2 +- arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi | 3 ++- arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi | 3 ++- 3 files changed, 5 insertions(+), 3 deletions(-) diff --git a/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi index 8d7dc0945ab..329dbd25dca 100644 --- a/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi +++ b/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi @@ -11,7 +11,7 @@ /{ aliases { spi0 = &qspi; - freeze_br0 = &freeze_controller; + freeze-br0 = &freeze_controller; }; soc { diff --git a/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi index 63df28e8364..51356a3fd41 100644 --- a/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi +++ b/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi @@ -3,6 +3,7 @@ * U-Boot additions * * Copyright (C) 2019-2022 Intel Corporation <www.intel.com> + * Copyright (C) 2025 Altera Corporation <www.altera.com> */ #include "socfpga_agilex-u-boot.dtsi" @@ -11,7 +12,7 @@ aliases { spi0 = &qspi; i2c0 = &i2c1; - freeze_br0 = &freeze_controller; + freeze-br0 = &freeze_controller; }; soc { diff --git a/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi index ef0df769762..a5b52ba33e4 100644 --- a/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi +++ b/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi @@ -3,6 +3,7 @@ * U-Boot additions * * Copyright (C) 2019-2022 Intel Corporation <www.intel.com> + * Copyright (C) 2025 Altera Corporation <www.altera.com> */ #include "socfpga_stratix10-u-boot.dtsi" @@ -10,7 +11,7 @@ /{ aliases { spi0 = &qspi; - freeze_br0 = &freeze_controller; + freeze-br0 = &freeze_controller; }; soc { -- 2.35.3
