On Tue, May 13, 2025 at 1:36 PM Dario Binacchi
<[email protected]> wrote:
> +static const struct dram_cfg_param ddr_ddrc_cfg_128mb[] = {
> + // IOMUX
> +
> + //DDR IO TYPE:
Same comment as in the previous patch.
> + //read data bit delay: 3 is the reccommended default value, although
> out of reset value is 0
recommended.
> + //Lower RALAT benefits:
> + //a. better operation at low frequency, for LPDDR2 freq < 100MHz,
> change RALAT to 3
> + //b. Small performence improvment
performance improvement
> + //MDMISC: RALAT kept to the high level of 5.
> + //MDMISC: consider reducing RALAT if your 528MHz board design allow
> that.
> + //Lower RALAT benefits:
> + //a. better operation at low frequency, for LPDDR2 freq < 100MHz,
> change RALAT to 3
> + //b. Small performence improvment
performance improvement.
> static void ddr_cfg_write(const struct dram_timing_info *dram_timing_info)
> {
> int i = 0;
You don't need to initialize i.
> +++ b/board/bsh/imx6ulz_smm_m2/spl_mtypes.h
> @@ -0,0 +1,26 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright 2025 BSH Hausgeraete GmbH
> + *
> + * Written by: Simon Holesch <[email protected]>
> + */
> +
> +#ifndef __SPL_BOARD__
> +#define __SPL_BOARD__
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