The clock initialization routine sets the DISP* clock parent to PLLC, resulting in DC failure in the case when PLLD was previously configured. This issue disrupts chainloading and to prevent failures caused by DISP* clock parent conflicts, clock initialization should not modify DISP*. The DC driver handles DISP* configuration.
Signed-off-by: Svyatoslav Ryhel <[email protected]> --- arch/arm/mach-tegra/tegra114/clock.c | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/mach-tegra/tegra114/clock.c b/arch/arm/mach-tegra/tegra114/clock.c index d5cc8ac44dd..d67d808b724 100644 --- a/arch/arm/mach-tegra/tegra114/clock.c +++ b/arch/arm/mach-tegra/tegra114/clock.c @@ -796,7 +796,6 @@ struct periph_clk_init periph_clk_init_table[] = { { PERIPH_ID_SBC5, CLOCK_ID_PERIPH }, { PERIPH_ID_SBC6, CLOCK_ID_PERIPH }, { PERIPH_ID_HOST1X, CLOCK_ID_PERIPH }, - { PERIPH_ID_DISP1, CLOCK_ID_CGENERAL }, { PERIPH_ID_NDFLASH, CLOCK_ID_PERIPH }, { PERIPH_ID_SDMMC1, CLOCK_ID_PERIPH }, { PERIPH_ID_SDMMC2, CLOCK_ID_PERIPH }, -- 2.43.0
