On Thu, 26 Sep 2024 10:25:00 +0530, Venkatesh Yadav Abbarapu wrote: > This series adds support for Xilinx qspi parallel and > stacked memeories. > > In parallel mode, the current implementation assumes that a maximum > of two flashes are connected. The QSPI controller splits the data > evenly between both the flashes so, both the flashes that are connected > in parallel mode should be identical. > During each operation SPI-NOR sets 0th bit for CS0 & 1st bit for CS1 in > nor->flags. > > [...]
Applied to u-boot/master, thanks! -- Tom
