On 10/5/24 7:45 PM, Marek Vasut wrote:
Tom, please pick this one directly for 2024.10 if possible. Or do you want a PR ?The SSCG is active with MDSEL[12] is not set. Previous commit 99c7e031196d ("clk: renesas: rcar-gen3: Replace SSCG caching with MDSEL/PE caching") inverted the conditional assignment of priv->sscg = !(cpg_mode & BIT(12)) during conversion from (priv->sscg ? 16 : 0) to priv->cpg_mode & BIT(core->offset) ? 16 : 0; Invert the assignment back to the correct state.This fixes R8A77980, R8A77990, R8A77995 and R8A774C0. Fixes: 99c7e031196d ("clk: renesas: rcar-gen3: Replace SSCG caching with MDSEL/PE caching") Signed-off-by: Marek Vasut <[email protected]> --- Cc: Tom Rini <[email protected]> --- NOTE: This is for 2024.10
