Hi Fabio, Primoz, Peng,
On 9/24/2024 10:56 AM, Peng Fan wrote:
Subject: Re: [PATCH 1/2] net: fec_mxc: Fix clk_ref rate on iMX93
Hi,
On 23. 09. 24 15:14, Peng Fan (OSS) wrote:
From: Ye Li <[email protected]>
Because iMX93 has a internal 1/2 divider before clock input to
network
controller, so have to set twice frequency rate
Fixes: 09de565f76b ("net: fec_mxc: support i.MX93")
Signed-off-by: Ye Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
---
drivers/net/fec_mxc.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index
0a0d92bc2cd..e5d7f0f3e1e 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -1215,6 +1215,9 @@ static int fecmxc_set_ref_clk(struct clk
*clk_ref, phy_interface_t interface)
else
return -EINVAL;
+ if (is_imx93())
+ freq = freq << 1;
Humm, but how did it work so far?
On phyboard-segin-imx93, this change breaks fec ethernet.
I had to revert this already in NXP downstream u-boot.
Ah. If you set enet_ref_clk to 250M, then you no need
this change. Otherwise you need this change.
Regards,
Peng.
Just check phyboard-segin-imx93, this board uses RMII not RGMII. It
outputs CCM clk_enet_ref on pin ENET1_TX_CLK to external phy for
reference clock and loop back it on pad to FEC as RMII clock. So this
usage has bypassed the 1/2 divider since the 1/2 divider is inside
wakeupmix not on path CCM clk_enet_ref to pad. We need to change the
patch to limit the 1/2 divider only for RGMII on iMX93.
In kernel, clk_enet_ref is assigned by dts, I don't see its rate changed
by driver like u-boot.
Best regards,
Ye Li
BR,
Primoz
+
ret = clk_set_rate(clk_ref, freq);
if (ret < 0)
return ret;
--
Primoz Fiser | phone: +386-41-390-545
<tel:+386-41-390-545> |
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