On Sat, Sep 24, 2022 at 11:06:24AM +1000, Jonathan Gray wrote: > On Fri, Sep 23, 2022 at 09:16:25AM -0500, Scott Cheloha wrote: > > [...] > > > > The only missing piece is code to read the configuration space on > > family 10h-16h CPUs to determine how many boosted P-states we need to > > skip to get to the MSR describing the software P0 state. I would > > really appreciate it if someone could explain how to do this at this > > very early point in boot. jsg@ pointed me to pci_conf_read(9), but > > I'm a little confused about how I get the needed pci* inputs at this > > point in boot. > > I also said you shouldn't be looking at pci devices for this.
Right, but the manual says that's where the information I want is located. I might be wrong, of course. Can't know until I get a test on a CPU in one of the relevant families. > I remain unconvinced that all of this is worth it compared to > calibrating off a timer with a known rate. For Intel CPUs we use CPUID to determine the TSC frequency where the leaf is available. It seems "fair," for lack of a better word, to make an effort to do the same for AMD CPUs. The other available timers with known frequencies are not great and they might be getting worse. The ISA timer is heavily gated out of the box on many contemporary machines where it is available. You can toggle the gating in the BIOS for now.The PM Timer and the HPET have been slow to read for years. I doubt these timers will improve. At minimum, I think it's safe to say that they are not a priority. They are considered "legacy" hardware, and you know what happens to the legacy stuff. Calibrating the TSC with one of these other timers introduces error: 1. jmc@'s machine (-0.187% error): cpu0: MSR C001_0064: en 1 base 200000000 mul 100 div 10 freq 2000000000 Hz tsc: calibrating with acpihpet0: 1996260074 Hz 2. robert@'s machine (-0.187% error): cpu0: MSR C001_0064: en 1 base 200000000 mul 156 div 8 freq 3900000000 Hz tsc: calibrating with acpihpet0: 3892696616 Hz 3. Timo Myrra's machine (-0.187% error): cpu0: MSR C001_0064: en 1 base 200000000 mul 100 div 10 freq 2000000000 Hz tsc: calibrating with acpihpet0: 1996264149 Hz The calibration code can be improved, and I have a patch waiting in the wings which does so, but you can't beat just *knowing* the frequency. ... I think we need to make the TSC "just work" in as many contexts as possible, especially on newer machines. > And it is the wrong time in the release cycle for this. This doesn't need to make release, I'm just gauging interest and testing code. > Boost could be disabled for the measurement if need by. > > AMD64 Architecture Programmer's Manual > Volume 2: System Programming > Publication No. 24593 > Revision 3.38 > > "17.2 Core Performance Boost > ... > CPB can be disabled using the CPBDis field of the Hardware Configuration > Register (HWCR MSR) on the appropriate core. When CPB is disabled, > hardware limits the frequency and voltage of the core to those defined > by P0. > > Support for core performance boost is indicated by > CPUID Fn8000_0007_EDX[CPB] = 1." > > "3.2.10 Hardware Configuration Register (HWCR) > ... > CpbDis. Bit 25. Core performance boost disable. When set to 1, core > performance boost is disabled. > " > > Processor Programming Reference (PPR) > for AMD Family 17h Model 01h, Revision B1 Processors > 54945 Rev 1.14 - April 15, 2017 > > "MSRC001_0015 [Hardware Configuration] (HWCR) > > 25 CpbDis: core performance boost disable. Read-write. > Reset: 0. 0=CPB is requested to be enabled. 1=CPB is disabled. > Specifies whether core performance boost is requested to be enabled or > disabled. If core performance boost is disabled while a core is in a > boosted P-state, the core automatically transitions to the highest > performance non-boosted P-state." > > [...] (Caveat: I might be wrong.) I believe this is only a toggle for whether the CPU can enter or remain in a boosted P-state. I do not think that toggling the feature on or off rewrites the P-state voltage/frequency MSRs on the fly. Toggling on or toggled off, we will still need a way to programmatically decide whether a given MSR describes a boosted P-state or P0. I have a line on a Sempron machine (family 10h) south of Austin, TX, $100. If it works when I pick it up I will probably have it set up to test within a few days.
