The below diff removes detection code for the Cyrix 486DLC and Cyrix 6x86 CPUs from OpenBSD/i386.
The Cyrix 486DLC is a 486-class CPU which we no longer support. The 6x86, also known as the M1, does not support CPUID by default. But it can be made to support this instruction if bit 7 in CCR4 is enabled. We don't do this in the tree today. The reason to remove support for the 6x86 is because it doesn't support the RDTSC instruction which we we use unconditionally. Therefore I don't believe Cyrix CPUs older than the 6x86MX (aka the M2) can run OpenBSD/i386. We keep the "cyrix6x86_cpu_setup" function in machdep because those quirks would still be needed on the M2. After this diff, the CPU detection code on i386 would assume that if the ID bit is missing from EFLAGS, we're running on an intel 486, while if we have the ID bit then we use the CPUID instruction for the detection logic. We also make the same change to amd64/include/specialreg.h to remove the defines for the Cyrix 486DLC. No Cyrix CPU supports amd64, so these defines have never made sense there. Index: i386/i386/locore0.S =================================================================== RCS file: /cvs/src/sys/arch/i386/i386/locore0.S,v retrieving revision 1.7 diff -u -p -u -r1.7 locore0.S --- i386/i386/locore0.S 15 Aug 2022 04:17:50 -0000 1.7 +++ i386/i386/locore0.S 20 Aug 2022 02:07:30 -0000 @@ -133,56 +133,6 @@ start: movw $0x1234,0x472 # warm boot jnz .Ltry586 .Lis486: movl $CPU_486,RELOC(_C_LABEL(cpu)) - /* - * Check Cyrix CPU - * Cyrix CPUs do not change the undefined flags following - * execution of the divide instruction which divides 5 by 2. - * - * Note: CPUID is enabled on M2, so it passes another way. - */ - pushfl - movl $0x5555, %eax - xorl %edx, %edx - movl $2, %ecx - clc - divl %ecx - jnc .Ltrycyrix486 - popfl - jmp 2f -.Ltrycyrix486: - movl $CPU_6x86,RELOC(_C_LABEL(cpu)) # set CPU type - /* - * Check for Cyrix 486 CPU by seeing if the flags change during a - * divide. This is documented in the Cx486SLC/e SMM Programmer's - * Guide. - */ - xorl %edx,%edx - cmpl %edx,%edx # set flags to known state - pushfl - popl %ecx # store flags in ecx - movl $-1,%eax - movl $4,%ebx - divl %ebx # do a long division - pushfl - popl %eax - xorl %ecx,%eax # are the flags different? - testl $0x8d5,%eax # only check C|PF|AF|Z|N|V - jne 2f # yes; must not be Cyrix CPU - movl $CPU_486DLC,RELOC(_C_LABEL(cpu)) # set CPU type - - /* Disable caching of the ISA hole only. */ - invd - movb $CCR0,%al # Configuration Register index (CCR0) - outb %al,$0x22 - inb $0x23,%al - orb $(CCR0_NC1|CCR0_BARB),%al - movb %al,%ah - movb $CCR0,%al - outb %al,$0x22 - movb %ah,%al - outb %al,$0x23 - invd - jmp 2f .Ltry586: /* Use the `cpuid' instruction. */ Index: i386/i386/machdep.c =================================================================== RCS file: /cvs/src/sys/arch/i386/i386/machdep.c,v retrieving revision 1.653 diff -u -p -u -r1.653 machdep.c --- i386/i386/machdep.c 18 Aug 2022 13:05:43 -0000 1.653 +++ i386/i386/machdep.c 20 Aug 2022 02:07:30 -0000 @@ -498,14 +498,8 @@ char cpu_model[120]; * We deal with the rest in a different way. */ const struct cpu_nocpuid_nameclass i386_nocpuid_cpus[] = { - { CPUVENDOR_INTEL, "Intel", "486SX", CPUCLASS_486, - NULL}, /* CPU_486SX */ { CPUVENDOR_INTEL, "Intel", "486DX", CPUCLASS_486, NULL}, /* CPU_486 */ - { CPUVENDOR_CYRIX, "Cyrix", "486DLC", CPUCLASS_486, - NULL}, /* CPU_486DLC */ - { CPUVENDOR_CYRIX, "Cyrix", "6x86", CPUCLASS_486, - cyrix6x86_cpu_setup}, /* CPU_6x86 */ }; const char *classnames[] = { @@ -2075,9 +2069,6 @@ identifycpu(struct cpu_info *ci) cpu_class = class; ci->cpu_class = class; - - if (cpu == CPU_486DLC) - printf("WARNING: CYRIX 486DLC CACHE UNCHANGED.\n"); /* * Enable ring 0 write protection. Index: i386/include/cputypes.h =================================================================== RCS file: /cvs/src/sys/arch/i386/include/cputypes.h,v retrieving revision 1.13 diff -u -p -u -r1.13 cputypes.h --- i386/include/cputypes.h 15 Aug 2022 04:17:51 -0000 1.13 +++ i386/include/cputypes.h 20 Aug 2022 02:07:30 -0000 @@ -37,19 +37,10 @@ #define CPUCLASS_686 3 /* - * Kinds of Processor. Only the first 7 are used, as they are processors - * that might not have a cpuid instruction. + * Kind of Processor. */ -#define CPU_486SX 2 /* Intel 80486SX */ -#define CPU_486 3 /* Intel 80486DX */ -#define CPU_486DLC 4 /* Cyrix 486DLC */ -#define CPU_6x86 5 /* Cyrix/IBM 6x86 */ -#define CPU_586 7 /* Intel P.....m (I hate lawyers; it's TM) */ -#define CPU_AM586 8 /* AMD Am486 and Am5x86 */ -#define CPU_K5 9 /* AMD K5 */ -#define CPU_K6 10 /* AMD K6 */ -#define CPU_686 11 /* Intel P.....m Pro */ +#define CPU_486 0 /* Intel 80486DX */ /* * CPU vendors Index: i386/include/specialreg.h =================================================================== RCS file: /cvs/src/sys/arch/i386/include/specialreg.h,v retrieving revision 1.79 diff -u -p -u -r1.79 specialreg.h --- i386/include/specialreg.h 21 Feb 2022 10:06:35 -0000 1.79 +++ i386/include/specialreg.h 20 Aug 2022 02:07:30 -0000 @@ -52,23 +52,6 @@ #define CR0_CD 0x40000000 /* Cache Disable */ /* - * Cyrix 486 DLC special registers, accessible as IO ports. - */ -#define CCR0 0xc0 /* configuration control register 0 */ -#define CCR0_NC0 0x01 /* first 64K of each 1M memory region is non-cacheable */ -#define CCR0_NC1 0x02 /* 640K-1M region is non-cacheable */ -#define CCR0_A20M 0x04 /* enables A20M# input pin */ -#define CCR0_KEN 0x08 /* enables KEN# input pin */ -#define CCR0_FLUSH 0x10 /* enables FLUSH# input pin */ -#define CCR0_BARB 0x20 /* flushes internal cache when entering hold state */ -#define CCR0_CO 0x40 /* cache org: 1=direct mapped, 0=2x set assoc */ -#define CCR0_SUSPEND 0x80 /* enables SUSP# and SUSPA# pins */ - -#define CCR1 0xc1 /* configuration control register 1 */ -#define CCR1_RPL 0x01 /* enables RPLSET and RPLVAL# pins */ -/* the remaining 7 bits of this register are reserved */ - -/* * bits in CR3 */ #define CR3_PWT (1ULL << 3) Index: amd64/include/specialreg.h =================================================================== RCS file: /cvs/src/sys/arch/amd64/include/specialreg.h,v retrieving revision 1.92 diff -u -p -u -r1.92 specialreg.h --- amd64/include/specialreg.h 26 Apr 2022 08:35:30 -0000 1.92 +++ amd64/include/specialreg.h 20 Aug 2022 02:07:30 -0000 @@ -53,23 +53,6 @@ #define CR0_CD 0x40000000 /* Cache Disable */ /* - * Cyrix 486 DLC special registers, accessible as IO ports. - */ -#define CCR0 0xc0 /* configuration control register 0 */ -#define CCR0_NC0 0x01 /* first 64K of each 1M memory region is non-cacheable */ -#define CCR0_NC1 0x02 /* 640K-1M region is non-cacheable */ -#define CCR0_A20M 0x04 /* enables A20M# input pin */ -#define CCR0_KEN 0x08 /* enables KEN# input pin */ -#define CCR0_FLUSH 0x10 /* enables FLUSH# input pin */ -#define CCR0_BARB 0x20 /* flushes internal cache when entering hold state */ -#define CCR0_CO 0x40 /* cache org: 1=direct mapped, 0=2x set assoc */ -#define CCR0_SUSPEND 0x80 /* enables SUSP# and SUSPA# pins */ - -#define CCR1 0xc1 /* configuration control register 1 */ -#define CCR1_RPL 0x01 /* enables RPLSET and RPLVAL# pins */ -/* the remaining 7 bits of this register are reserved */ - -/* * bits in CR3 */ #define CR3_PCID 0xfffULL