Hi, For long long time, I detached TX382B based UART board and recently I reinstalled it.
John Kelly's report "TXIC TX382B UART controller support" (https://marc.info/?l=openbsd-tech&m=147352668517825) says this controller sometimes lacks THRE interrupt, I found the symptom. I did self loopback (connect TX382B's TXD and RXD) test at that time. This test cannot detect that problem. Connecting with other UART such as USB-UART can be seen TX-hang of TX382B. I tried with enabling TX382B's fifo, the problem could be avoided so this might work as workaround. Reported LSR related issue is not solved yet because I could not reproduce the problem (is there any good method?). This is future tasks. Here is the diff to enable TX382's FIFO. Sorry for this problem is kept unresolved for long time. Index: ic/com.c =================================================================== RCS file: /cvs/src/sys/dev/ic/com.c,v retrieving revision 1.174 diff -u -r1.174 com.c --- ic/com.c 6 May 2021 20:35:21 -0000 1.174 +++ ic/com.c 30 May 2021 00:41:43 -0000 @@ -1480,6 +1480,11 @@ SET(sc->sc_hwflags, COM_HW_FIFO); sc->sc_fifolen = 256; break; + case COM_UART_TX382B: + printf(": tx382b, 16 byte fifo\n"); + SET(sc->sc_hwflags, COM_HW_FIFO); + sc->sc_fifolen = 16; + break; default: panic("comattach: bad fifo type"); } @@ -1487,7 +1492,8 @@ #ifdef COM_CONSOLE if (!ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) #endif - if (sc->sc_fifolen < 256) + if (sc->sc_uarttype != COM_UART_TX382B && + sc->sc_fifolen < 256) com_fifo_probe(sc); if (sc->sc_fifolen == 0) { Index: ic/comvar.h =================================================================== RCS file: /cvs/src/sys/dev/ic/comvar.h,v retrieving revision 1.58 diff -u -r1.58 comvar.h --- ic/comvar.h 14 Aug 2020 18:14:11 -0000 1.58 +++ ic/comvar.h 30 May 2021 00:41:43 -0000 @@ -104,6 +104,7 @@ #define COM_UART_XR16850 0x10 /* 128 byte fifo */ #define COM_UART_OX16C950 0x11 /* 128 byte fifo */ #define COM_UART_XR17V35X 0x12 /* 256 byte fifo */ +#define COM_UART_TX382B 0x13 /* 16 byte fifo, no loopback */ u_char sc_hwflags; #define COM_HW_NOIEN 0x01 Index: pci/pucdata.c =================================================================== RCS file: /cvs/src/sys/dev/pci/pucdata.c,v retrieving revision 1.114 diff -u -r1.114 pucdata.c --- pci/pucdata.c 19 May 2021 05:28:09 -0000 1.114 +++ pci/pucdata.c 30 May 2021 00:41:44 -0000 @@ -2259,8 +2259,8 @@ { PCI_VENDOR_TXIC, PCI_PRODUCT_TXIC_TX382B, 0, 0 }, { 0xffff, 0xffff, 0, 0 }, { - { PUC_PORT_COM, 0x10, 0x0000 }, - { PUC_PORT_COM, 0x14, 0x0000 }, + { PUC_PORT_COM_TX382B, 0x10, 0x0000 }, + { PUC_PORT_COM_TX382B, 0x14, 0x0000 }, } }, { /* "ASIX AX99100", */ Index: pci/pucvar.h =================================================================== RCS file: /cvs/src/sys/dev/pci/pucvar.h,v retrieving revision 1.17 diff -u -r1.17 pucvar.h --- pci/pucvar.h 14 Aug 2020 18:14:11 -0000 1.17 +++ pci/pucvar.h 30 May 2021 00:41:44 -0000 @@ -61,6 +61,7 @@ PUC_PORT_COM_MUL10, PUC_PORT_COM_MUL128, PUC_PORT_COM_XR17V35X, + PUC_PORT_COM_TX382B, } type; u_int32_t freq; }; @@ -73,6 +74,7 @@ { PUC_PORT_COM_MUL10, COM_FREQ * 10 }, { PUC_PORT_COM_MUL128, COM_FREQ * 128 }, { PUC_PORT_COM_XR17V35X, 125000000 }, + { PUC_PORT_COM_TX382B, COM_FREQ }, }; #define PUC_IS_LPT(type) ((type) == PUC_PORT_LPT) Index: puc/com_puc.c =================================================================== RCS file: /cvs/src/sys/dev/puc/com_puc.c,v retrieving revision 1.26 diff -u -r1.26 com_puc.c --- puc/com_puc.c 5 Mar 2021 13:20:19 -0000 1.26 +++ puc/com_puc.c 30 May 2021 00:41:44 -0000 @@ -105,8 +105,17 @@ break; } - if (pa->type == PUC_PORT_COM_XR17V35X) + switch (pa->type) { + case PUC_PORT_COM_XR17V35X: sc->sc_uarttype = COM_UART_XR17V35X; + break; + case PUC_PORT_COM_TX382B: + sc->sc_uarttype = COM_UART_TX382B; + break; + default: + /* do nothing */ + break; + } com_attach_subr(sc); } -- SASANO Takayoshi (JG1UAA) <u...@mx5.nisiq.net>
