athn(4): Set frame's Tx duration and power

[Stefan Sperling]

Linux ath9k provides Tx time of an entire frame to hardware.
Make our athn(4) driver do the same.

ALso set registers which contain Tx power values for retried frames.

Please test.

diff 8885fdfe4213e1feed4da2ad98226517b33cdcf5 /usr/src
blob - 1890ab7d38911a4917ed03869d7cc734669506cb
file + sys/dev/ic/ar5008.c
--- sys/dev/ic/ar5008.c
+++ sys/dev/ic/ar5008.c
@@ -1550,12 +1550,11 @@ ar5008_tx(struct athn_softc *sc, struct mbuf *m, struc
                    ridx[i] != ATHN_RIDX_CCK1 &&
                    (ic->ic_flags & IEEE80211_F_SHPREAMBLE))
                        series[i].hwrate |= 0x04;
-               series[i].dur = 0;
-       }
-       if (!(ds->ds_ctl1 & AR_TXC1_NO_ACK)) {
                /* Compute duration for each series. */
-               for (i = 0; i < 4; i++) {
-                       series[i].dur = athn_txtime(sc, IEEE80211_ACK_LEN,
+               series[i].dur = athn_txtime(sc, totlen, ridx[i], ic->ic_flags);
+               if (!(ds->ds_ctl1 & AR_TXC1_NO_ACK)) {
+                       /* Account for ACK duration. */
+                       series[i].dur += athn_txtime(sc, IEEE80211_ACK_LEN,
                            athn_rates[ridx[i]].rspridx, ic->ic_flags);
                }
        }
@@ -1600,6 +1599,11 @@ ar5008_tx(struct athn_softc *sc, struct mbuf *m, struc
        if (ic->ic_flags & IEEE80211_F_CBW40)
                ds->ds_ctl7 |= AR_TXC7_2040_0123;
 #endif
+
+       /* Set Tx power for series 1 - 3 */
+       ds->ds_ctl9 = SM(AR_TXC9_XMIT_POWER1, txpower);
+       ds->ds_ctl10 = SM(AR_TXC10_XMIT_POWER2, txpower);
+       ds->ds_ctl11 = SM(AR_TXC11_XMIT_POWER3, txpower);
 
        if (ds->ds_ctl0 & (AR_TXC0_RTS_ENABLE | AR_TXC0_CTS_ENABLE)) {
                uint8_t protridx, hwrate;
blob - 91349bcbee6f9a5443115c77f09fe5454f25e783
file + sys/dev/ic/ar5008reg.h
--- sys/dev/ic/ar5008reg.h
+++ sys/dev/ic/ar5008reg.h
@@ -809,6 +809,18 @@ struct ar_tx_desc {
 #define AR_TXC7_GI0123         \
        (AR_TXC7_GI0 | AR_TXC7_GI1 | AR_TXC7_GI2 | AR_TXC7_GI3)
 
+/* Bits for ds_ctl9. */
+#define AR_TXC9_XMIT_POWER1_M          0x3f000000
+#define AR_TXC9_XMIT_POWER1_S          24
+
+/* Bits for ds_ctl10. */
+#define AR_TXC10_XMIT_POWER2_M         0x3f000000
+#define AR_TXC10_XMIT_POWER2_S         24
+
+/* Bits for ds_ctl11. */
+#define AR_TXC11_XMIT_POWER3_M         0x3f000000
+#define AR_TXC11_XMIT_POWER3_S         24
+
 /* Bits for ds_status0. */
 #define AR_TXS0_RSSI_ANT0(i)           (((x) >> ((i) * 8)) & 0xff)
 #define AR_TXS0_BA_STATUS              0x40000000