Hi all,
The patch below works fine for me and fixes the
*[ERROR: ath0 unable to reset hardware]* issue that I had on my
FUJITSU SIEMENS ESPRIMO Mobile U9210.
Patch is relative to -current.
Please check.
Many Thanks Stefan Sperling
for Code Review and strong support with Copyright!
Oleg Pahl
(Munich)
On 10/06/18 14:28, Stefan Sperling wrote:
On Sat, Oct 06, 2018 at 01:32:55PM +0200, NN wrote:
Hi all,
Many thanks for your support and reply!
I am not Profi (I have experience < 1year with OpenBSD and C Programming.),
that why its will take me a lot of time to fix and try something.
After Mr. Sperling first review of my Code ... I have made few fixes.
In attachment you can see my new patch. Please, try it and send me your
feedback.
Its working for me. (*no more ERROR: ath0 unable to reset hardware*)
Thank you! This is looking great. I see only two remaining problems:
Please don't use C++-style // comments. The lines commented this way
can just be removed.
More importantly it looks like these changes are based on work done
by Nick Kossifidis in Linux ath5k. I am quoting the relevant changes
from the Linux git log below. So I doubt this is your original work.
It is OK to copy this code into OpenBSD because it is licensed under
ISC, the same licence used by our ath(4) driver which this Linux code
was based on. But only under the condition that we give attribution
to the original author. So please copy Nick's copyright line into our
files as well. You can find it at the top of each file you've copied
code from.
And then we should be good to go.
commit cc6323c7d8c231d83e592ff9f7acf2cac5e016f7
Author: Nick Kossifidis <m...@madwifi.org>
Date: Sun Jul 20 06:44:43 2008 +0300
ath5k: Update channel functions
* Add channel function for RF2425 (got this from decompiling binary
HAL, i have no idea why there is a 5GHz section but i'm looking
into it)
* Update RF5112 channel function (also got this from decompiling binary
HAL)
* Set JAPAN setting for channel 14 on all PHY chips
Changes-licensed-under: ISC
Signed-off-by: Nick Kossifidis <mickfl...@gmail.com>
Signed-off-by: John W. Linville <linvi...@tuxdriver.com>
diff --git a/drivers/net/wireless/ath5k/phy.c b/drivers/net/wireless/ath5k/phy.c
index 66af70bd14e7..cbc362d20719 100644
--- a/drivers/net/wireless/ath5k/phy.c
+++ b/drivers/net/wireless/ath5k/phy.c
@@ -1898,9 +1898,6 @@ static int ath5k_hw_rf5112_channel(struct ath5k_hw *ah,
data = data0 = data1 = data2 = 0;
c = channel->center_freq;
- /*
- * Set the channel on the RF5112 or newer
- */
if (c < 4800) {
if (!((c - 2224) % 5)) {
data0 = ((2 * (c - 704)) - 3040) / 10;
@@ -1912,7 +1909,7 @@ static int ath5k_hw_rf5112_channel(struct ath5k_hw *ah,
return -EINVAL;
data0 = ath5k_hw_bitswap((data0 << 2) & 0xff, 8);
- } else {
+ } else if ((c - (c % 5)) != 2 || c > 5435) {
if (!(c % 20) && c >= 5120) {
data0 = ath5k_hw_bitswap(((c - 4800) / 20 << 2), 8);
data2 = ath5k_hw_bitswap(3, 2);
@@ -1924,6 +1921,9 @@ static int ath5k_hw_rf5112_channel(struct ath5k_hw *ah,
data2 = ath5k_hw_bitswap(1, 2);
} else
return -EINVAL;
+ } else {
+ data0 = ath5k_hw_bitswap((10 * (c - 2) - 4800) / 25 + 1, 8);
+ data2 = ath5k_hw_bitswap(0, 2);
}
data = (data0 << 4) | (data1 << 1) | (data2 << 2) | 0x1001;
@@ -1934,6 +1934,45 @@ static int ath5k_hw_rf5112_channel(struct ath5k_hw *ah,
return 0;
}
+/*
+ * Set the channel on the RF2425
+ */
+static int ath5k_hw_rf2425_channel(struct ath5k_hw *ah,
+ struct ieee80211_channel *channel)
+{
+ u32 data, data0, data2;
+ u16 c;
+
+ data = data0 = data2 = 0;
+ c = channel->center_freq;
+
+ if (c < 4800) {
+ data0 = ath5k_hw_bitswap((c - 2272), 8);
+ data2 = 0;
+ /* ? 5GHz ? */
+ } else if ((c - (c % 5)) != 2 || c > 5435) {
+ if (!(c % 20) && c < 5120)
+ data0 = ath5k_hw_bitswap(((c - 4800) / 20 << 2), 8);
+ else if (!(c % 10))
+ data0 = ath5k_hw_bitswap(((c - 4800) / 10 << 1), 8);
+ else if (!(c % 5))
+ data0 = ath5k_hw_bitswap((c - 4800) / 5, 8);
+ else
+ return -EINVAL;
+ data2 = ath5k_hw_bitswap(1, 2);
+ } else {
+ data0 = ath5k_hw_bitswap((10 * (c - 2) - 4800) / 25 + 1, 8);
+ data2 = ath5k_hw_bitswap(0, 2);
+ }
+
+ data = (data0 << 4) | data2 << 2 | 0x1001;
+
+ ath5k_hw_reg_write(ah, data & 0xff, AR5K_RF_BUFFER);
+ ath5k_hw_reg_write(ah, (data >> 8) & 0x7f, AR5K_RF_BUFFER_CONTROL_5);
+
+ return 0;
+}
+
/*
* Set a channel on the radio chip
*/
@@ -1963,6 +2002,9 @@ int ath5k_hw_channel(struct ath5k_hw *ah, struct
ieee80211_channel *channel)
case AR5K_RF5111:
ret = ath5k_hw_rf5111_channel(ah, channel);
break;
+ case AR5K_RF2425:
+ ret = ath5k_hw_rf2425_channel(ah, channel);
+ break;
default:
ret = ath5k_hw_rf5112_channel(ah, channel);
break;
@@ -1971,6 +2013,15 @@ int ath5k_hw_channel(struct ath5k_hw *ah, struct
ieee80211_channel *channel)
if (ret)
return ret;
+ /* Set JAPAN setting for channel 14 */
+ if (channel->center_freq == 2484) {
commit 1889ba0a48688b639c2b2e9e1b0fd8f84e2c37d1
Author: Nick Kossifidis <m...@madwifi-project.org>
Date: Thu Apr 30 15:55:46 2009 -0400
ath5k: Put remaining EEPROM data on ee struct
* Put remaining EEPROM information on ee struct and remove is_hb63
function.
Now we also have rfkill stuff available.
Signed-off-by: Nick Kossifidis <mickfl...@gmail.com>
Signed-off-by: Bob Copeland <m...@bobcopeland.com>
Signed-off-by: John W. Linville <linvi...@tuxdriver.com>
diff --git a/drivers/net/wireless/ath/ath5k/eeprom.c
b/drivers/net/wireless/ath/ath5k/eeprom.c
index 587c5b8ddc2c..8c9dd019d761 100644
--- a/drivers/net/wireless/ath/ath5k/eeprom.c
+++ b/drivers/net/wireless/ath/ath5k/eeprom.c
@@ -156,6 +156,17 @@ ath5k_eeprom_init_header(struct ath5k_hw *ah)
ee->ee_db[AR5K_EEPROM_MODE_11G][0] = (val >> 3) & 0x7;
}
+ AR5K_EEPROM_READ(AR5K_EEPROM_IS_HB63, val);
+
+ if ((ah->ah_mac_version == (AR5K_SREV_AR2425 >> 4)) && val)
+ ee->ee_is_hb63 = true;
+ else
+ ee->ee_is_hb63 = false;
+
+ AR5K_EEPROM_READ(AR5K_EEPROM_RFKILL, val);
+ ee->ee_rfkill_pin = (u8) AR5K_REG_MS(val, AR5K_EEPROM_RFKILL_GPIO_SEL);
+ ee->ee_rfkill_pol = val & AR5K_EEPROM_RFKILL_POLARITY ? true : false;
+
return 0;
}
@@ -1789,16 +1800,3 @@ int ath5k_eeprom_read_mac(struct ath5k_hw *ah, u8 *mac)
return 0;
}
-
-bool ath5k_eeprom_is_hb63(struct ath5k_hw *ah)
-{
- u16 data;
-
- ath5k_hw_eeprom_read(ah, AR5K_EEPROM_IS_HB63, &data);
-
- if ((ah->ah_mac_version == (AR5K_SREV_AR2425 >> 4)) && data)
- return true;
- else
- return false;
-}
-
diff --git a/drivers/net/wireless/ath/ath5k/eeprom.h
b/drivers/net/wireless/ath/ath5k/eeprom.h
index df9ffa044ea6..46e4d22591f6 100644
--- a/drivers/net/wireless/ath/ath5k/eeprom.h
+++ b/drivers/net/wireless/ath/ath5k/eeprom.h
@@ -26,6 +26,13 @@
#define AR5K_EEPROM_MAGIC_5210 0x0000145a /* 5210 */
#define AR5K_EEPROM_IS_HB63 0x000b /* Talon detect */
+
+#define AR5K_EEPROM_RFKILL 0x0f
+#define AR5K_EEPROM_RFKILL_GPIO_SEL 0x0000001c
+#define AR5K_EEPROM_RFKILL_GPIO_SEL_S 2
+#define AR5K_EEPROM_RFKILL_POLARITY 0x00000002
+#define AR5K_EEPROM_RFKILL_POLARITY_S 1
+
#define AR5K_EEPROM_REG_DOMAIN 0x00bf /* EEPROM regdom */
#define AR5K_EEPROM_CHECKSUM 0x00c0 /* EEPROM checksum */
#define AR5K_EEPROM_INFO_BASE 0x00c0 /* EEPROM header */
@@ -66,11 +73,6 @@
#define AR5K_EEPROM_HDR_RFKILL(_v) (((_v) >> 14) & 0x1) /* Device has
RFKill support */
#define AR5K_EEPROM_HDR_T_5GHZ_DIS(_v) (((_v) >> 15) & 0x1) /*
Disable turbo for 5Ghz */
-#define AR5K_EEPROM_RFKILL_GPIO_SEL 0x0000001c
-#define AR5K_EEPROM_RFKILL_GPIO_SEL_S 2
-#define AR5K_EEPROM_RFKILL_POLARITY 0x00000002
-#define AR5K_EEPROM_RFKILL_POLARITY_S 1
-
/* Newer EEPROMs are using a different offset */
#define AR5K_EEPROM_OFF(_v, _v3_0, _v3_3) \
(((_v) >= AR5K_EEPROM_VERSION_3_3) ? _v3_3 : _v3_0)
@@ -386,6 +388,9 @@ struct ath5k_eeprom_info {
u16 ee_version;
u16 ee_header;
u16 ee_ant_gain;
+ u8 ee_rfkill_pin;
+ bool ee_rfkill_pol;
+ bool ee_is_hb63;
u16 ee_misc0;
u16 ee_misc1;
u16 ee_misc2;
diff --git a/drivers/net/wireless/ath/ath5k/reset.c
b/drivers/net/wireless/ath/ath5k/reset.c
index cb8a9a1398c9..d419c6a3ded7 100644
--- a/drivers/net/wireless/ath/ath5k/reset.c
+++ b/drivers/net/wireless/ath/ath5k/reset.c
@@ -507,7 +507,7 @@ static void ath5k_hw_set_sleep_clock(struct ath5k_hw *ah,
bool enable)
if (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))
scal = AR5K_PHY_SCAL_32MHZ_2417;
- else if (ath5k_eeprom_is_hb63(ah))
+ else if (ee->ee_is_hb63)
scal = AR5K_PHY_SCAL_32MHZ_HB63;
else
scal = AR5K_PHY_SCAL_32MHZ;
@@ -598,9 +598,10 @@ static void ath5k_hw_tweak_initval_settings(struct
ath5k_hw *ah,
/* Set DAC/ADC delays */
if (ah->ah_version == AR5K_AR5212) {
u32 scal;
+ struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
if (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))
scal = AR5K_PHY_SCAL_32MHZ_2417;
- else if (ath5k_eeprom_is_hb63(ah))
+ else if (ee->ee_is_hb63)
scal = AR5K_PHY_SCAL_32MHZ_HB63;
else
scal = AR5K_PHY_SCAL_32MHZ;
Index: ar5212.c
===================================================================
RCS file: /cvs/src/sys/dev/ic/ar5212.c,v
retrieving revision 1.59
diff -u -p -u -p -r1.59 ar5212.c
--- ar5212.c 3 Feb 2018 17:17:31 -0000 1.59
+++ ar5212.c 17 Oct 2018 21:23:44 -0000
@@ -2,6 +2,7 @@
/*
* Copyright (c) 2004, 2005, 2006, 2007 Reyk Floeter <r...@openbsd.org>
+ * Copyright (c) 2008-2009 Nick Kossifidis <mickfl...@gmail.com>
*
* Permission to use, copy, modify, and distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
@@ -235,10 +236,17 @@ ar5k_ar5212_attach(u_int16_t device, voi
hal->ah_phy_spending = AR5K_AR5212_PHY_SPENDING_AR5424;
hal->ah_radio_5ghz_revision = hal->ah_radio_2ghz_revision =
AR5K_SREV_VER_AR5413;
- } else if (srev == AR5K_SREV_VER_AR2425) {
+ } else if (hal->ah_mac_version == (AR5K_SREV_VER_AR2425 >> 4) ||
+ hal->ah_mac_version == (AR5K_SREV_VER_AR2417 >> 4) ||
+ hal->ah_phy_revision == (AR5K_SREV_PHY_2425)) {
hal->ah_radio = AR5K_AR2425;
- hal->ah_phy_spending = AR5K_AR5212_PHY_SPENDING_AR5112;
+ hal->ah_single_chip = AH_TRUE;
hal->ah_radio_5ghz_revision = AR5K_SREV_RAD_SC2;
+ } else if ((hal->ah_mac_version == (AR5K_SREV_VER_AR2424 >> 4)) ||
+ (hal->ah_phy_revision == AR5K_SREV_PHY_5413)) {
+ hal->ah_radio = AR5K_AR5413;
+ hal->ah_single_chip = AH_TRUE;
+ hal->ah_radio_5ghz_revision = AR5K_SREV_RAD_5413;
} else if (hal->ah_radio_5ghz_revision < AR5K_SREV_RAD_5112) {
hal->ah_radio = AR5K_AR5111;
hal->ah_phy_spending = AR5K_AR5212_PHY_SPENDING_AR5111;
@@ -2871,10 +2879,8 @@ ar5k_ar5212_get_capabilities(struct ath_
if (b)
hal->ah_capabilities.cap_mode |= HAL_MODE_11B;
-#if 0
if (g)
hal->ah_capabilities.cap_mode |= HAL_MODE_11G;
-#endif
}
/* GPIO */
Index: ar5212reg.h
===================================================================
RCS file: /cvs/src/sys/dev/ic/ar5212reg.h,v
retrieving revision 1.12
diff -u -p -u -p -r1.12 ar5212reg.h
--- ar5212reg.h 30 Jul 2008 07:15:39 -0000 1.12
+++ ar5212reg.h 17 Oct 2018 21:23:44 -0000
@@ -2,6 +2,7 @@
/*
* Copyright (c) 2004, 2005, 2006, 2007 Reyk Floeter <r...@openbsd.org>
+ * Copyright (c) 2008-2009 Nick Kossifidis <mickfl...@gmail.com>
*
* Permission to use, copy, modify, and distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
@@ -456,6 +457,7 @@
*/
#define AR5K_AR5212_DCU_MISC(_n) AR5K_AR5212_DCU(_n, 0x1100)
#define AR5K_AR5212_DCU_MISC_BACKOFF 0x000007ff
+#define AR5K_AR5212_DCU_MISC_FRAG_WAIT 0x00000100
#define AR5K_AR5212_DCU_MISC_BACKOFF_FRAG 0x00000200
#define AR5K_AR5212_DCU_MISC_HCFPOLL_ENABLE 0x00000800
#define AR5K_AR5212_DCU_MISC_BACKOFF_PERSIST 0x00001000
@@ -1099,6 +1101,8 @@ typedef enum {
#define AR5K_AR5212_PHY_SLMT_32MHZ 0x0000007f
#define AR5K_AR5212_PHY_SCAL 0x9878
#define AR5K_AR5212_PHY_SCAL_32MHZ 0x0000000e
+#define AR5K_AR5212_PHY_SCAL_32MHZ_2417 0x0000000a
+#define AR5K_AR5212_PHY_SCAL_32MHZ_HB63 0x00000032
/*
* PHY PLL control register
Index: ar5xxx.c
===================================================================
RCS file: /cvs/src/sys/dev/ic/ar5xxx.c,v
retrieving revision 1.63
diff -u -p -u -p -r1.63 ar5xxx.c
--- ar5xxx.c 31 Jan 2018 11:27:03 -0000 1.63
+++ ar5xxx.c 17 Oct 2018 21:23:44 -0000
@@ -2,6 +2,7 @@
/*
* Copyright (c) 2004, 2005, 2006, 2007 Reyk Floeter <r...@openbsd.org>
+ * Copyright (c) 2008-2009 Nick Kossifidis <mickfl...@gmail.com>
*
* Permission to use, copy, modify, and distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
@@ -86,6 +87,7 @@ u_int32_t ar5k_ar5110_chan2athchan(HAL_
HAL_BOOL ar5k_ar5111_channel(struct ath_hal *, HAL_CHANNEL *);
HAL_BOOL ar5k_ar5111_chan2athchan(u_int, struct ar5k_athchan_2ghz *);
HAL_BOOL ar5k_ar5112_channel(struct ath_hal *, HAL_CHANNEL *);
+HAL_BOOL ar5k_ar2425_channel(struct ath_hal *, HAL_CHANNEL *);
HAL_BOOL ar5k_check_channel(struct ath_hal *, u_int16_t, u_int flags);
HAL_BOOL ar5k_ar5111_rfregs(struct ath_hal *, HAL_CHANNEL *, u_int);
@@ -889,6 +891,13 @@ ar5k_eeprom_init(struct ath_hal *hal)
ee->ee_ob[AR5K_EEPROM_MODE_11G][0] = val & 0x7;
ee->ee_db[AR5K_EEPROM_MODE_11G][0] = (val >> 3) & 0x7;
}
+
+ AR5K_EEPROM_READ(AR5K_EEPROM_IS_HB63, val);
+
+ if ((hal->ah_mac_version == (AR5K_SREV_VER_AR2425 >> 4)) && val)
+ ee->ee_is_hb63 = AH_TRUE;
+ else
+ ee->ee_is_hb63 = AH_FALSE;
/*
* Get conformance test limit values
@@ -1109,6 +1118,8 @@ ar5k_channel(struct ath_hal *hal, HAL_CH
ret = ar5k_ar5110_channel(hal, channel);
else if (hal->ah_radio == AR5K_AR5111)
ret = ar5k_ar5111_channel(hal, channel);
+ else if (hal->ah_radio == AR5K_AR2425)
+ ret = ar5k_ar2425_channel(hal, channel);
else
ret = ar5k_ar5112_channel(hal, channel);
@@ -1263,6 +1274,45 @@ ar5k_ar5112_channel(struct ath_hal *hal,
AR5K_PHY_WRITE(0x27, data & 0xff);
AR5K_PHY_WRITE(0x36, (data >> 8) & 0x7f);
+
+ return (AH_TRUE);
+}
+
+HAL_BOOL
+ar5k_ar2425_channel(struct ath_hal *hal, HAL_CHANNEL *channel)
+{
+ u_int32_t data, data0, data2;
+ u_int16_t c;
+
+ data = data0 = data2 = 0;
+ c = channel->c_channel + hal->ah_chanoff;
+
+ /*
+ * Set the channel on the AR2425
+ */
+ if (c < 4800) {
+ data0 = ar5k_bitswap((c - 2272), 8);
+ data2 = 0;
+ } else if ((c - (c % 5)) != 2 || c > 5435) {
+ if (!(c % 20) && c < 5120)
+ data0 = ar5k_bitswap(((c - 4800) / 20 << 2), 8);
+ else if (!(c % 10))
+ data0 = ar5k_bitswap(((c - 4800) / 10 << 1), 8);
+ else if (!(c % 5))
+ data0 = ar5k_bitswap((c - 4800) / 5, 8);
+ else
+ return (AH_FALSE);
+
+ data2 = ar5k_bitswap(1, 2);
+ } else {
+ data0 = ar5k_bitswap((10 * (c - 2) - 4800) / 25 + 1, 8);
+ data2 = ar5k_bitswap(0, 2);
+ }
+
+ data = (data0 << 4) | (data2 << 2) | 0x1001;
+
+ AR5K_PHY_WRITE(0x27, data & 0xff);
+ AR5K_PHY_WRITE(0x36, (data >> 8) & 0x7f);
return (AH_TRUE);
}
Index: ar5xxx.h
===================================================================
RCS file: /cvs/src/sys/dev/ic/ar5xxx.h,v
retrieving revision 1.60
diff -u -p -u -p -r1.60 ar5xxx.h
--- ar5xxx.h 25 Aug 2017 12:17:27 -0000 1.60
+++ ar5xxx.h 17 Oct 2018 21:23:45 -0000
@@ -2,6 +2,7 @@
/*
* Copyright (c) 2004, 2005, 2006, 2007 Reyk Floeter <r...@openbsd.org>
+ * Copyright (c) 2008-2009 Nick Kossifidis <mickfl...@gmail.com>
*
* Permission to use, copy, modify, and distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
@@ -623,6 +624,8 @@ struct ar5k_gain {
#define AR5K_EEPROM_INFO_CKSUM 0xffff
#define AR5K_EEPROM_INFO(_n) (AR5K_EEPROM_INFO_BASE + (_n))
+#define AR5K_EEPROM_IS_HB63 0x000b /* Talon detect */
+
#define AR5K_EEPROM_VERSION AR5K_EEPROM_INFO(1)
#define AR5K_EEPROM_VERSION_3_0 0x3000
#define AR5K_EEPROM_VERSION_3_1 0x3001
@@ -765,6 +768,8 @@ struct ar5k_eeprom_info {
int16_t ee_noise_floor_thr[AR5K_EEPROM_N_MODES];
int8_t ee_adc_desired_size[AR5K_EEPROM_N_MODES];
int8_t ee_pga_desired_size[AR5K_EEPROM_N_MODES];
+
+ HAL_BOOL ee_is_hb63;
};
/*
@@ -1235,7 +1240,9 @@ struct ar5k_srev_name {
#define AR5K_SREV_VER_AR5414 0xa5
#define AR5K_SREV_VER_AR5416 0xc0 /* PCI-Express */
#define AR5K_SREV_VER_AR5418 0xca /* PCI-Express */
-#define AR5K_SREV_VER_AR2425 0xe2 /* PCI-Express */
+#define AR5K_SREV_VER_AR2425 0xe0 /* PCI-Express (Swan, was 0xe2) */
+#define AR5K_SREV_VER_AR2417 0xf0 /* PCI-Express (Nala) */
+
#define AR5K_SREV_VER_UNSUPP 0xff
#define AR5K_SREV_RAD_5110 0x00
@@ -1249,8 +1256,12 @@ struct ar5k_srev_name {
#define AR5K_SREV_RAD_SC0 0x56
#define AR5K_SREV_RAD_SC1 0x63
#define AR5K_SREV_RAD_SC2 0xa2
+#define AR5K_SREV_RAD_5413 0x60
+#define AR5K_SREV_RAD_2425 0xa2
#define AR5K_SREV_RAD_5133 0xc0
#define AR5K_SREV_RAD_UNSUPP 0xff
+#define AR5K_SREV_PHY_5413 0x61
+#define AR5K_SREV_PHY_2425 0x70
#define AR5K_DEVID_AR2413 0x001a
#define AR5K_DEVID_AR5413 0x001b
