> Date: Sat, 13 Jan 2018 23:08:55 +0000 > From: Dimitris Papastamos <s...@2f30.org> > > > + case CPU_ID_CORTEX_A15: > > + case CPU_ID_CORTEX_A57: > > + case CPU_ID_CORTEX_A72: > > + /* > > + * Vulnerable; BPIALL is "not effective" so must use > > + * ICIALLU and hope the firmware set the magic bit in > > + * the ACTLR that actually forces a BTB flush. > > + */ > > + ci->ci_flush_bp = cortex_a15_flush_bp; > > + break; > > + } > > Unfortunately there is an A57 erratum (833069) that when "Disabling > MMU Translation with CPUACTLR_EL1 "Enable Invalidates of BTB" bit set > can cause Invalidate by PA or VA to fail". The only safe way to > trigger BTB invalidation on A57 is to disable and enable the MMU.
Thanks for the heads-up. I remember reading that erratum thinking "that sucks", and then forgot about it. I'll leave Cortex-A57 out for now and will revisit this once I have the PSCI call implemented. Running OpenBSD/armv7 on Cortex-A57 is largely academic anyway.
