> Date: Wed, 10 Aug 2016 22:53:03 -0300 > From: Daniel Bolgheroni <dbolgher...@gmail.com> > > On Thu, Aug 11, 2016 at 02:30:59AM +0200, Mark Kettenis wrote: > > Finally found the pmap bug that kept Cortex-A7 from working. Turns > > out we have to flush the TLB when removing a L1 slot as well. Already > > committed the diff, but here it is for those that are interested. > > This diff makes Cubieboard2 to break earlier. > > Copyright (c) 1982, 1986, 1989, 1991, 1993 > The Regents of the University of California. All rights reserved. > Copyright (c) 1995-2016 OpenBSD. All rights reserved. http://www.OpenBSD.org > > OpenBSD 6.0-current (RAMDISK) #6: Wed Aug 10 22:37:03 BRT 2016 > dbolgher...@wbs.my.domain:/usr/src/sys/arch/armv7/compile/RAMDISK > real mem = 1073741824 (1024MB) > avail mem = 1038749696 (990MB) > mainbus0 at root: Cubietech Cubieboard2 > cpu0 at mainbus0: ARM Cortex A7 rev 4 (ARMv7 core) > cpu0: DC enabled IC enabled WB disabled EABT branch prediction enabled > cpu0: 32KB(32b/l,2way) I-cache, 32KB(64b/l,4way) wr-back D-cache > cortex0 at mainbus0 > > uvm_fault(0xc0cddc50, 81a3f000, 1, 0) -> e > Fatal kernel mode data abort: 'Translation Fault (S)' > trapframe: 0xc0daad18 > DFSR=00000005, DFAR=81a3fef8, spsr=200001d3 > r0 =81a3fef8, r1 =00000001, r2 =c0daad88, r3 =c0c94c70 > r4 =c04f0dc0, r5 =c0daad88, r6 =c04f1088, r7 =c05102a8 > r8 =c0c92aa8, r9 =00000000, r10=c0daae64, r11=c0daad84 > r12=c0daad88, ssp=c0daad6c, slr=c040ae6c, pc =c040abb8
You probably forgot to run "make config" before rebuilding your kernel.
