Hello,
This patch adds a debugging function dumping the contents of all
registers implicated in the armv7/imx specific sd/mmc controller. It
only prints if the kernel is built with option SDHC_DEBUG and a call is
inserted somewhere.
I am trying to fix the outstanding bug causing the imxesdhc driver to
timeout upon block reads (CMD17) which prevents any meaningful I/O with
"disks" on i.MX6 platforms. If anyone has any helpful pointers to this
end, please respond on-list or to i...@kremlin.cc
Thanks,
Ian
Index: imx/imxesdhc.c
===================================================================
RCS file: /cvs/src/sys/arch/armv7/imx/imxesdhc.c,v
retrieving revision 1.12
diff -u -p -r1.12 imxesdhc.c
--- imx/imxesdhc.c 30 May 2015 03:20:54 -0000 1.12
+++ imx/imxesdhc.c 7 Nov 2015 00:50:08 -0000
@@ -208,11 +208,76 @@ void imxesdhc_read_data(struct imxesdhc_
void imxesdhc_write_data(struct imxesdhc_softc *, u_char *, int);
//#define SDHC_DEBUG
+void imxesdhc_dump_regs(struct imxesdhc_softc *);
#ifdef SDHC_DEBUG
int imxesdhcdebug = 20;
#define DPRINTF(n,s) do { if ((n) <= imxesdhcdebug) printf s; } while (0)
+void
+imxesdhc_dump_regs(struct imxesdhc_softc *sc)
+{
+ DPRINTF(3, ("%s: SDHC_DS_ADDR: 0x%08x\n",
+ DEVNAME(sc), HREAD4(sc, SDHC_DS_ADDR)));
+ DPRINTF(3, ("%s: SDHC_BLK_ATT: 0x%08x\n",
+ DEVNAME(sc), HREAD4(sc, SDHC_BLK_ATT)));
+ DPRINTF(3, ("%s: SDHC_CMD_ARG: 0x%08x\n",
+ DEVNAME(sc), HREAD4(sc, SDHC_CMD_ARG)));
+ DPRINTF(3, ("%s: SDHC_CMD_XFR_TYP: 0x%08x\n",
+ DEVNAME(sc), HREAD4(sc, SDHC_CMD_XFR_TYP)));
+ DPRINTF(3, ("%s: SDHC_CMD_RSP0: 0x%08x\n",
+ DEVNAME(sc), HREAD4(sc, SDHC_CMD_RSP0)));
+ DPRINTF(3, ("%s: SDHC_CMD_RSP1: 0x%08x\n",
+ DEVNAME(sc), HREAD4(sc, SDHC_CMD_RSP1)));
+ DPRINTF(3, ("%s: SDHC_CMD_RSP2: 0x%08x\n",
+ DEVNAME(sc), HREAD4(sc, SDHC_CMD_RSP2)));
+ DPRINTF(3, ("%s: SDHC_CMD_RSP3: 0x%08x\n",
+ DEVNAME(sc), HREAD4(sc, SDHC_CMD_RSP3)));
+ DPRINTF(3, ("%s: SDHC_DATA_BUFF_ACC_PORT: 0x%08x\n",
+ DEVNAME(sc), HREAD4(sc, SDHC_DATA_BUFF_ACC_PORT)));
+ DPRINTF(3, ("%s: SDHC_PRES_STATE: 0x%08x\n",
+ DEVNAME(sc), HREAD4(sc, SDHC_PRES_STATE)));
+ DPRINTF(3, ("%s: SDHC_PROT_CTRL: 0x%08x\n",
+ DEVNAME(sc), HREAD4(sc, SDHC_PROT_CTRL)));
+ DPRINTF(3, ("%s: SDHC_SYS_CTRL: 0x%08x\n",
+ DEVNAME(sc), HREAD4(sc, SDHC_SYS_CTRL)));
+ DPRINTF(3, ("%s: SDHC_INT_STATUS: 0x%08x\n",
+ DEVNAME(sc), HREAD4(sc, SDHC_INT_STATUS)));
+ DPRINTF(3, ("%s: SDHC_INT_STATUS_EN: 0x%08x\n",
+ DEVNAME(sc), HREAD4(sc, SDHC_INT_STATUS_EN)));
+ DPRINTF(3, ("%s: SDHC_INT_SIGNAL_EN: 0x%08x\n",
+ DEVNAME(sc), HREAD4(sc, SDHC_INT_SIGNAL_EN)));
+ DPRINTF(3, ("%s: SDHC_AUTOCMD12_ERR_STATUS: 0x%08x\n",
+ DEVNAME(sc), HREAD4(sc, SDHC_AUTOCMD12_ERR_STATUS)));
+ DPRINTF(3, ("%s: SDHC_HOST_CTRL_CAP: 0x%08x\n",
+ DEVNAME(sc), HREAD4(sc, SDHC_HOST_CTRL_CAP)));
+ DPRINTF(3, ("%s: SDHC_WTMK_LVL: 0x%08x\n",
+ DEVNAME(sc), HREAD4(sc, SDHC_WTMK_LVL)));
+ DPRINTF(3, ("%s: SDHC_MIX_CTRL: 0x%08x\n",
+ DEVNAME(sc), HREAD4(sc, SDHC_MIX_CTRL)));
+ DPRINTF(3, ("%s: SDHC_FORCE_EVENT: 0x%08x\n",
+ DEVNAME(sc), HREAD4(sc, SDHC_FORCE_EVENT)));
+ DPRINTF(3, ("%s: SDHC_ADMA_ERR_STATUS: 0x%08x\n",
+ DEVNAME(sc), HREAD4(sc, SDHC_ADMA_ERR_STATUS)));
+ DPRINTF(3, ("%s: SDHC_ADMA_SYS_ADDR: 0x%08x\n",
+ DEVNAME(sc), HREAD4(sc, SDHC_ADMA_SYS_ADDR)));
+ DPRINTF(3, ("%s: SDHC_DLL_CTRL: 0x%08x\n",
+ DEVNAME(sc), HREAD4(sc, SDHC_DLL_CTRL)));
+ DPRINTF(3, ("%s: SDHC_DLL_STATUS: 0x%08x\n",
+ DEVNAME(sc), HREAD4(sc, SDHC_DLL_STATUS)));
+ DPRINTF(3, ("%s: SDHC_CLK_TUNE_CTRL_STATUS: 0x%08x\n",
+ DEVNAME(sc), HREAD4(sc, SDHC_CLK_TUNE_CTRL_STATUS)));
+ DPRINTF(3, ("%s: SDHC_VEND_SPEC: 0x%08x\n",
+ DEVNAME(sc), HREAD4(sc, SDHC_VEND_SPEC)));
+ DPRINTF(3, ("%s: SDHC_MMC_BOOT: 0x%08x\n",
+ DEVNAME(sc), HREAD4(sc, SDHC_MMC_BOOT)));
+ DPRINTF(3, ("%s: SDHC_VEND_SPEC2: 0x%08x\n",
+ DEVNAME(sc), HREAD4(sc, SDHC_VEND_SPEC2)));
+ DPRINTF(3, ("%s: SDHC_HOST_CTRL_VER: 0x%08x\n",
+ DEVNAME(sc), HREAD4(sc, SDHC_HOST_CTRL_VER)));
+}
#else
#define DPRINTF(n,s) do {} while(0)
+void
+imxesdhc_dump_regs(struct imxesdhc_softc *sc) {}
#endif
struct sdmmc_chip_functions imxesdhc_functions = {
