> Date: Thu, 15 Oct 2015 01:03:10 +0200 (CEST)
> From: si...@slackware.it
>
> Hello tech@,
> I'm sorry for resurrecting an old thread: I'm seeing intel drm errors in my
> dmesg, they appeared with the same end of September -current snapshot as the
> original poster mentioned but I'm having no visible issues other than some
> noise in the logs.
> Hardware is an EeePC 701 (i915) running i386 -current, here's dmesg from 13th
> October snapshot:
>
...
> error: [drm:pid0:i915_gem_detect_bit_6_swizzle] *ERROR* Couldn't read from
> MCHBAR. Disabling tiling.
Hmm, does the diff below help?
Index: drm_linux.h
===================================================================
RCS file: /home/cvs/src/sys/dev/pci/drm/drm_linux.h,v
retrieving revision 1.41
diff -u -p -r1.41 drm_linux.h
--- drm_linux.h 27 Sep 2015 21:28:14 -0000 1.41
+++ drm_linux.h 15 Oct 2015 18:20:53 -0000
@@ -971,6 +971,10 @@ struct dmi_system_id {
#define DMI_EXACT_MATCH(a, b) {(a), (b)}
int dmi_check_system(const struct dmi_system_id *);
+struct resource {
+ u_long start;
+};
+
struct pci_dev {
uint16_t vendor;
uint16_t device;
Index: i915/i915_dma.c
===================================================================
RCS file: /home/cvs/src/sys/dev/pci/drm/i915/i915_dma.c,v
retrieving revision 1.23
diff -u -p -r1.23 i915_dma.c
--- i915/i915_dma.c 23 Sep 2015 23:12:11 -0000 1.23
+++ i915/i915_dma.c 15 Oct 2015 19:15:44 -0000
@@ -1128,6 +1128,17 @@ static int i915_get_bridge_dev(struct dr
}
return 0;
}
+#else
+int i915_get_bridge_dev(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+
+ dev_priv->bridge_dev = malloc(sizeof(*dev_priv->bridge_dev),
+ M_DEVBUF, M_WAITOK);
+ dev_priv->bridge_dev->pc = dev->pdev->pc;
+ dev_priv->bridge_dev->tag = pci_make_tag(dev->pdev->pc, 0, 0, 0);
+ return 0;
+}
#endif
#define MCHBAR_I915 0x44
@@ -1145,35 +1156,29 @@ intel_alloc_mchbar_resource(struct drm_d
int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
u32 temp_lo, temp_hi = 0;
u64 mchbar_addr;
- u_long addr;
if (INTEL_INFO(dev)->gen >= 4)
- temp_hi = pci_conf_read(dev_priv->pc, dev_priv->tag, reg + 4);
- temp_lo = pci_conf_read(dev_priv->pc, dev_priv->tag, reg);
+ pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
+ pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
- if (mchbar_addr == 0) {
- addr = (u_long)mchbar_addr;
- if (dev_priv->memex == NULL || extent_alloc(dev_priv->memex,
- MCHBAR_SIZE, MCHBAR_SIZE, 0, 0, 0, &addr)) {
- return -ENOMEM;
- } else {
- mchbar_addr = addr;
- /* We've allocated it, now fill in the BAR again */
- if (INTEL_INFO(dev)->gen >= 4)
- pci_conf_write(dev_priv->pc, dev_priv->tag,
- reg + 4, upper_32_bits(mchbar_addr));
- pci_conf_write(dev_priv->pc, dev_priv->tag,
- reg, lower_32_bits(mchbar_addr));
- }
+ if (mchbar_addr &&
+ extent_alloc_region(dev_priv->memex, mchbar_addr, MCHBAR_SIZE,
+ EX_NOWAIT) == 0)
+ return 0;
+
+ /* Get some space for it */
+ if (dev_priv->memex == NULL || extent_alloc(dev_priv->memex,
+ MCHBAR_SIZE, MCHBAR_SIZE, 0, 0, 0, &dev_priv->mch_res.start)) {
+ return -ENOMEM;
}
if (INTEL_INFO(dev)->gen >= 4)
- pci_conf_write(dev_priv->pc, dev_priv->tag, reg + 4,
- upper_32_bits(mchbar_addr));
+ pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
+ upper_32_bits(dev_priv->mch_res.start));
- pci_conf_write(dev_priv->pc, dev_priv->tag, reg,
- lower_32_bits(mchbar_addr));
+ pci_write_config_dword(dev_priv->bridge_dev, reg,
+ lower_32_bits(dev_priv->mch_res.start));
return 0;
}
@@ -1183,16 +1188,16 @@ intel_setup_mchbar(struct drm_device *de
{
drm_i915_private_t *dev_priv = dev->dev_private;
int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
- pcireg_t temp;
+ u32 temp;
bool enabled;
dev_priv->mchbar_need_disable = false;
if (IS_I915G(dev) || IS_I915GM(dev)) {
- temp = pci_conf_read(dev_priv->pc, dev_priv->tag, DEVEN_REG);
+ pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
enabled = !!(temp & DEVEN_MCHBAR_EN);
} else {
- temp = pci_conf_read(dev_priv->pc, dev_priv->tag, mchbar_reg);
+ pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
enabled = temp & 1;
}
@@ -1207,11 +1212,11 @@ intel_setup_mchbar(struct drm_device *de
/* Space is allocated or reserved, so enable it. */
if (IS_I915G(dev) || IS_I915GM(dev)) {
- pci_conf_write(dev_priv->pc, dev_priv->tag, DEVEN_REG,
- temp | DEVEN_MCHBAR_EN);
+ pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG,
+ temp | DEVEN_MCHBAR_EN);
} else {
- temp = pci_conf_read(dev_priv->pc, dev_priv->tag, mchbar_reg);
- pci_conf_write(dev_priv->pc, dev_priv->tag, mchbar_reg, temp |
1);
+ pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
+ pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp |
1);
}
}
@@ -1220,28 +1225,23 @@ intel_teardown_mchbar(struct drm_device
{
drm_i915_private_t *dev_priv = dev->dev_private;
int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
- pcireg_t temp;
- u_int64_t mchbar_addr;
- pcireg_t low, high = 0;
+ u32 temp;
if (dev_priv->mchbar_need_disable) {
if (IS_I915G(dev) || IS_I915GM(dev)) {
- temp = pci_conf_read(dev_priv->pc, dev_priv->tag,
DEVEN_REG);
+ pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG,
&temp);
temp &= ~DEVEN_MCHBAR_EN;
- pci_conf_write(dev_priv->pc, dev_priv->tag, DEVEN_REG,
temp);
+ pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG,
temp);
} else {
- temp = pci_conf_read(dev_priv->pc, dev_priv->tag,
mchbar_reg);
+ pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg,
&temp);
temp &= ~1;
- pci_conf_write(dev_priv->pc, dev_priv->tag, mchbar_reg,
temp);
+ pci_write_config_dword(dev_priv->bridge_dev,
mchbar_reg, temp);
}
}
- if (INTEL_INFO(dev)->gen >= 4)
- high = pci_conf_read(dev_priv->pc, dev_priv->tag, mchbar_reg +
4);
- low = pci_conf_read(dev_priv->pc, dev_priv->tag, mchbar_reg);
- mchbar_addr = ((u_int64_t)high << 32) | low;
- if (dev_priv->memex)
- extent_free(dev_priv->memex, mchbar_addr, MCHBAR_SIZE, 0);
+ if (dev_priv->mch_res.start)
+ extent_free(dev_priv->memex, dev_priv->mch_res.start,
+ MCHBAR_SIZE, 0);
}
#ifdef __linux__
Index: i915/i915_drv.c
===================================================================
RCS file: /home/cvs/src/sys/dev/pci/drm/i915/i915_drv.c,v
retrieving revision 1.93
diff -u -p -r1.93 i915_drv.c
--- i915/i915_drv.c 28 Sep 2015 17:29:56 -0000 1.93
+++ i915/i915_drv.c 15 Oct 2015 19:11:35 -0000
@@ -197,6 +197,7 @@ void i965_alloc_ifp(struct inteldrm_soft
void intel_gtt_chipset_setup(struct drm_device *);
/* i915_dma.c */
+int i915_get_bridge_dev(struct drm_device *);
void intel_setup_mchbar(struct drm_device *);
void intel_teardown_mchbar(struct drm_device *);
int i915_load_modeset_init(struct drm_device *);
@@ -1240,12 +1241,12 @@ inteldrm_attach(struct device *parent, s
if (IS_HSW_EARLY_SDV(dev))
DRM_INFO("This is an early pre-production Haswell machine. "
"It may not be fully functional.\n");
+#endif
if (i915_get_bridge_dev(dev)) {
ret = -EIO;
goto free_priv;
}
-#endif
mmio_bar = IS_GEN2(dev) ? 1 : 0;
/* Before gen4, the registers and the GTT are behind different BARs.
Index: i915/i915_drv.h
===================================================================
RCS file: /home/cvs/src/sys/dev/pci/drm/i915/i915_drv.h,v
retrieving revision 1.69
diff -u -p -r1.69 i915_drv.h
--- i915/i915_drv.h 28 Sep 2015 17:29:56 -0000 1.69
+++ i915/i915_drv.h 15 Oct 2015 18:21:05 -0000
@@ -1498,9 +1498,7 @@ typedef struct inteldrm_softc {
uint32_t last_seqno, next_seqno;
drm_dma_handle_t *status_page_dmah;
-#ifdef __linux__
struct resource mch_res;
-#endif
union flush {
struct {
bus_space_tag_t bst;
