> Date: Sat, 21 May 2011 17:08:07 -0400 > From: Brynet <bry...@gmail.com> > > On Sat, May 21, 2011 at 10:32:01PM +0200, Mark Kettenis wrote: > > > Date: Thu, 19 May 2011 19:09:36 -0400 > > > From: Brynet <bry...@gmail.com> > > > > > > Here it is a again with the magic relocated to piixreg.h. > > > > > > To clarify, if you have: > > > piixpm0 at pci0 dev 20 function 0 "ATI SBx00 SMBus" > > > > > > Then check if the revision is >= 0x40, which is the relevant southbridge. > > > > > > If it works, you'll see pretty stuff like this:: > > > spdmem0 at iic addr 0x50: 2GB DDR3 SDRAM PC3-10600 SO-DIMM > > > .. > > > > Had a look at the chipset docs, and it took me some time to figure out > > how AMD had hidden these registers away. So I wrote a somewhat less cryptic > > comment that explains the code a bit better. I also noticed that there is > > a register that indicates whether SMI is enabled or not. > > > > So here's a cleaned up diff. Does this still work for you? > > It does indeed, thanks for the help.
Cool! Anybody around who can test this diff on a machine with non-AMD piixpm(4)?
