This upstream patch courtesy of Chris Wilson <ch...@chirs-wilson.co.uk> both limits tied pitches to 8192 on pre-i965 and enables switching from one VT to another without terminating your Xsession. :)
Tested on a Thinkpad X301 with an Aug 3 amd64 snapshot.. Please see http://cgit.freedesktop.org/mesa/drm/commit/?id=726210f87d558d558022f35bc8c839e798a19f0c --- intel_bufmgr_gem.c.orig Wed Aug 4 06:42:44 2010 +++ intel_bufmgr_gem.c Wed Aug 4 07:07:44 2010 @@ -252,7 +252,7 @@ */ static unsigned long drm_intel_gem_bo_tile_pitch(drm_intel_bufmgr_gem *bufmgr_gem, - unsigned long pitch, uint32_t tiling_mode) + unsigned long pitch, uint32_t *tiling_mode) { unsigned long tile_width; unsigned long i; @@ -260,10 +260,10 @@ /* If untiled, then just align it so that we can do rendering * to it with the 3D engine. */ - if (tiling_mode == I915_TILING_NONE) + if (*tiling_mode == I915_TILING_NONE) return ALIGN(pitch, 64); - if (tiling_mode == I915_TILING_X) + if (*tiling_mode == I915_TILING_X) tile_width = 512; else tile_width = 128; @@ -272,6 +272,14 @@ if (bufmgr_gem->gen >= 4) return ROUND_UP_TO(pitch, tile_width); + /* The older hardware has a maximum pitch of 8192 with tiled + * surfaces, so fallback to untiled if it's too large. + */ + if (pitch > 8192) { + *tiling_mode = I915_TILING_NONE; + return ALIGN(pitch, 64); +} + /* Pre-965 needs power of two tile width */ for (i = tile_width; i < pitch; i <<= 1) ; @@ -679,7 +687,7 @@ stride = x * cpp; stride = drm_intel_gem_bo_tile_pitch(bufmgr_gem, stride, *tiling_mode); size = stride * aligned_y; - size = drm_intel_gem_bo_tile_size(bufmgr_gem, size, tiling_mode); + size = drm_intel_gem_bo_tile_size(bufmgr_gem, size, *tiling_mode); bo = drm_intel_gem_bo_alloc_internal(bufmgr, name, size, flags); if (!bo)
