While looking at eephy(4) I noticed that we're toggling the wrong bit
to enable auto crossover on the 88E3016 and 88E3082 PHYs. This diff
fixes that, but since this changes the bits we set, I'd like some
people to test this. Note that this only needs to be tested on
machines with 100baseTX variants of msk(4), i.e. those that have:
eephy0 at msk0 phy 0: 88E3016 10/100 PHY, rev. 0
or
eephy0 at msk0 phy 0: 88E3082 10/100 PHY, rev. 3
Thanks,
Mark
Index: eephy.c
===================================================================
RCS file: /cvs/src/sys/dev/mii/eephy.c,v
retrieving revision 1.48
diff -N -u -p eephy.c
--- eephy.c 4 Jun 2009 05:19:38 -0000 1.48
+++ eephy.c 4 Jun 2009 05:36:27 -0000
@@ -207,8 +207,7 @@ eephyattach(struct device *parent, struct device *self
switch (sc->mii_model) {
case MII_MODEL_MARVELL_E3016:
case MII_MODEL_MARVELL_E3082:
- /* Bits are in a different position. */
- reg |= (E1000_SCR_AUTO_X_MODE >> 1);
+ reg |= E3000_SCR_AUTO_X_MODE;
break;
default:
/* Automatic crossover causes problems for 1000baseX. */
@@ -216,6 +215,7 @@ eephyattach(struct device *parent, struct device *self
reg &= ~E1000_SCR_AUTO_X_MODE;
else
reg |= E1000_SCR_AUTO_X_MODE;
+ break;
}
/* Disable energy detect; only available on some models. */
Index: eephyreg.h
===================================================================
RCS file: /cvs/src/sys/dev/mii/eephyreg.h,v
retrieving revision 1.7
diff -N -u -p eephyreg.h
--- eephyreg.h 4 Jun 2009 05:19:38 -0000 1.7
+++ eephyreg.h 4 Jun 2009 05:36:27 -0000
@@ -233,6 +233,7 @@
#define E1000_SCR_EN_DETECT_MASK 0x0300
+#define E3000_SCR_AUTO_X_MODE 0x0020
#define E3000_SCR_SCRAMBLER_DISABLE 0x0200
#define E3000_SCR_REG8_NEXT_PAGE 0x1000
#define E3000_SCR_EN_DETECT_MASK 0x4000
