Minimal stable backport of f227d4306cf30e1d5b6f231e8ef9006c34f3d186. In certain cases the kernel can set up an interrupt vector for error thresholding that is different from the LvtOffset of bank 4. This leads to a misconfiguration of the mce threshold lvt offset and in particular to a setup failure of the ibs interrupt since there is an lvt offset conflict:
[Firmware Bug]: cpu 2, try to use APIC500 (LVT offset 0) for vector 0x10400, but the register is already in use for vector 0xf9 on another cpu [Firmware Bug]: cpu 2, IBS interrupt offset 0 not available (MSRC001103A=0x0000000000000100) Failed to setup IBS, -22 Fix this by always taking the lvt offset from bank 4. Cc: <[email protected]> # v3.0 Cc: Borislav Petkov <[email protected]> Signed-off-by: Robert Richter <[email protected]> --- arch/x86/kernel/cpu/mcheck/mce_amd.c | 4 ++++ 1 files changed, 4 insertions(+), 0 deletions(-) diff --git a/arch/x86/kernel/cpu/mcheck/mce_amd.c b/arch/x86/kernel/cpu/mcheck/mce_amd.c index 99b5717..76aebc5 100644 --- a/arch/x86/kernel/cpu/mcheck/mce_amd.c +++ b/arch/x86/kernel/cpu/mcheck/mce_amd.c @@ -174,6 +174,10 @@ void mce_amd_feature_init(struct cpuinfo_x86 *c) unsigned int bank, block; int offset = -1; + /* initialize lvt offset from bank 4 */ + rdmsr_safe(MSR_IA32_MC0_MISC + 16, &low, &high); + offset = setup_APIC_mce(offset, (high & MASK_LVTOFF_HI) >> 20); + for (bank = 0; bank < NR_BANKS; ++bank) { for (block = 0; block < NR_BLOCKS; ++block) { if (block == 0) -- 1.7.8.4 -- To unsubscribe from this list: send the line "unsubscribe stable" in the body of a message to [email protected] More majordomo info at http://vger.kernel.org/majordomo-info.html
