This is a note to let you know that I've just added the patch titled
hwmon: (zl6100) Enable interval between chip accesses for all chips
to the 3.2-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
hwmon-zl6100-enable-interval-between-chip-accesses-for-all-chips.patch
and it can be found in the queue-3.2 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree,
please let <[email protected]> know about it.
>From fecfb64422d91a9621a3f96ab75c3a5f13e80b58 Mon Sep 17 00:00:00 2001
From: Guenter Roeck <[email protected]>
Date: Tue, 13 Mar 2012 09:05:14 -0700
Subject: hwmon: (zl6100) Enable interval between chip accesses for all chips
From: Guenter Roeck <[email protected]>
commit fecfb64422d91a9621a3f96ab75c3a5f13e80b58 upstream.
Intersil reports that all chips supported by the zl6100 driver require
an interval between chip accesses, even ZL2004 and ZL6105 which were thought
to be safe.
Reported-by: Vivek Gani <[email protected]>
Signed-off-by: Guenter Roeck <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
---
Documentation/hwmon/zl6100 | 14 ++++++--------
drivers/hwmon/pmbus/zl6100.c | 11 +++--------
2 files changed, 9 insertions(+), 16 deletions(-)
--- a/Documentation/hwmon/zl6100
+++ b/Documentation/hwmon/zl6100
@@ -73,14 +73,12 @@ Module parameters
delay
-----
-Some Intersil/Zilker Labs DC-DC controllers require a minimum interval between
-I2C bus accesses. According to Intersil, the minimum interval is 2 ms, though
-1 ms appears to be sufficient and has not caused any problems in testing.
-The problem is known to affect ZL6100, ZL2105, and ZL2008. It is known not to
-affect ZL2004 and ZL6105. The driver automatically sets the interval to 1 ms
-except for ZL2004 and ZL6105. To enable manual override, the driver provides a
-writeable module parameter, 'delay', which can be used to set the interval to
-a value between 0 and 65,535 microseconds.
+Intersil/Zilker Labs DC-DC controllers require a minimum interval between I2C
+bus accesses. According to Intersil, the minimum interval is 2 ms, though 1 ms
+appears to be sufficient and has not caused any problems in testing. The
problem
+is known to affect all currently supported chips. For manual override, the
+driver provides a writeable module parameter, 'delay', which can be used to set
+the interval to a value between 0 and 65,535 microseconds.
Sysfs entries
--- a/drivers/hwmon/pmbus/zl6100.c
+++ b/drivers/hwmon/pmbus/zl6100.c
@@ -178,16 +178,11 @@ static int zl6100_probe(struct i2c_clien
data->id = mid->driver_data;
/*
- * ZL2008, ZL2105, and ZL6100 are known to require a wait time
- * between I2C accesses. ZL2004 and ZL6105 are known to be safe.
- *
- * Only clear the wait time for chips known to be safe. The wait time
- * can be cleared later for additional chips if tests show that it
- * is not needed (in other words, better be safe than sorry).
+ * According to information from the chip vendor, all currently
+ * supported chips are known to require a wait time between I2C
+ * accesses.
*/
data->delay = delay;
- if (data->id == zl2004 || data->id == zl6105)
- data->delay = 0;
/*
* Since there was a direct I2C device access above, wait before
Patches currently in stable-queue which might be from
[email protected] are
queue-3.2/hwmon-zl6100-enable-interval-between-chip-accesses-for-all-chips.patch
queue-3.2/hwmon-w83627ehf-fix-temp2-source-for-w83627uhg.patch
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