This is a note to let you know that I've just added the patch titled
ARM: 7356/1: perf: check that we have an event in the PMU IRQ handlers
to the 3.2-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
arm-7356-1-perf-check-that-we-have-an-event-in-the-pmu-irq-handlers.patch
and it can be found in the queue-3.2 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree,
please let <[email protected]> know about it.
>From f6f5a30c834135c9f2fa10400c59ebbdd9188567 Mon Sep 17 00:00:00 2001
From: Will Deacon <[email protected]>
Date: Tue, 6 Mar 2012 17:34:50 +0100
Subject: ARM: 7356/1: perf: check that we have an event in the PMU IRQ handlers
From: Will Deacon <[email protected]>
commit f6f5a30c834135c9f2fa10400c59ebbdd9188567 upstream.
The PMU IRQ handlers in perf assume that if a counter has overflowed
then perf must be responsible. In the paranoid world of crazy hardware,
this could be false, so check that we do have a valid event before
attempting to dereference NULL in the interrupt path.
Signed-off-by: Ming Lei <[email protected]>
Signed-off-by: Will Deacon <[email protected]>
Signed-off-by: Russell King <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
---
arch/arm/kernel/perf_event_v6.c | 20 ++------------------
arch/arm/kernel/perf_event_v7.c | 4 ++++
arch/arm/kernel/perf_event_xscale.c | 6 ++++++
3 files changed, 12 insertions(+), 18 deletions(-)
--- a/arch/arm/kernel/perf_event_v6.c
+++ b/arch/arm/kernel/perf_event_v6.c
@@ -463,23 +463,6 @@ armv6pmu_enable_event(struct hw_perf_eve
raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
}
-static int counter_is_active(unsigned long pmcr, int idx)
-{
- unsigned long mask = 0;
- if (idx == ARMV6_CYCLE_COUNTER)
- mask = ARMV6_PMCR_CCOUNT_IEN;
- else if (idx == ARMV6_COUNTER0)
- mask = ARMV6_PMCR_COUNT0_IEN;
- else if (idx == ARMV6_COUNTER1)
- mask = ARMV6_PMCR_COUNT1_IEN;
-
- if (mask)
- return pmcr & mask;
-
- WARN_ONCE(1, "invalid counter number (%d)\n", idx);
- return 0;
-}
-
static irqreturn_t
armv6pmu_handle_irq(int irq_num,
void *dev)
@@ -509,7 +492,8 @@ armv6pmu_handle_irq(int irq_num,
struct perf_event *event = cpuc->events[idx];
struct hw_perf_event *hwc;
- if (!counter_is_active(pmcr, idx))
+ /* Ignore if we don't have an event. */
+ if (!event)
continue;
/*
--- a/arch/arm/kernel/perf_event_v7.c
+++ b/arch/arm/kernel/perf_event_v7.c
@@ -1029,6 +1029,10 @@ static irqreturn_t armv7pmu_handle_irq(i
struct perf_event *event = cpuc->events[idx];
struct hw_perf_event *hwc;
+ /* Ignore if we don't have an event. */
+ if (!event)
+ continue;
+
/*
* We have a single interrupt for all counters. Check that
* each counter has overflowed before we process it.
--- a/arch/arm/kernel/perf_event_xscale.c
+++ b/arch/arm/kernel/perf_event_xscale.c
@@ -253,6 +253,9 @@ xscale1pmu_handle_irq(int irq_num, void
struct perf_event *event = cpuc->events[idx];
struct hw_perf_event *hwc;
+ if (!event)
+ continue;
+
if (!xscale1_pmnc_counter_has_overflowed(pmnc, idx))
continue;
@@ -590,6 +593,9 @@ xscale2pmu_handle_irq(int irq_num, void
struct perf_event *event = cpuc->events[idx];
struct hw_perf_event *hwc;
+ if (!event)
+ continue;
+
if (!xscale2_pmnc_counter_has_overflowed(pmnc, idx))
continue;
Patches currently in stable-queue which might be from [email protected] are
queue-3.2/arm-7357-1-perf-fix-overflow-handling-for-xscale2-pmus.patch
queue-3.2/arm-7356-1-perf-check-that-we-have-an-event-in-the-pmu-irq-handlers.patch
queue-3.2/arm-7355-1-perf-clear-overflow-flag-when-disabling-counter-on-armv7-pmu.patch
queue-3.2/arm-7345-1-errata-update-workaround-for-a9-erratum-743622.patch
queue-3.2/arm-7354-1-perf-limit-sample_period-to-half-max_period-in-non-sampling-mode.patch
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