On 2023-08-29 12:03, Uma Shankar wrote:
Add the documentation for the new proposed Plane Color Pipeline.
Co-developed-by: Chaitanya Kumar Borah
Signed-off-by: Chaitanya Kumar Borah
Signed-off-by: Uma Shankar
---
.../gpu/rfc/plane_color_pipeline.rst | 394 ++
1 f
+CC Naseer and Chris, FYI
See https://patchwork.freedesktop.org/series/123024/ for whole series.
On 2023-08-29 12:03, Uma Shankar wrote:
Introduction
Modern hardwares have various color processing capabilities both
at pre-blending and post-blending phases in the color pipeline.
Th
From: Chaitanya Kumar Borah
Initialize and expose all plane color features.
Co-developed-by: Uma Shankar
Signed-off-by: Uma Shankar
Signed-off-by: Chaitanya Kumar Borah
---
drivers/gpu/drm/i915/display/intel_color.c | 1 -
drivers/gpu/drm/i915/display/skl_universal_plane.c | 1 +
2 f
From: Chaitanya Kumar Borah
This patch is to demonstrate how a pipeline can be added.
Co-developed-by: Uma Shankar
Signed-off-by: Uma Shankar
Signed-off-by: Chaitanya Kumar Borah
---
drivers/gpu/drm/drm_atomic_state_helper.c | 3 ++
drivers/gpu/drm/drm_atomic_uapi.c | 15 +
Implement plane CSC for Xe_LPD.
Co-developed-by: Chaitanya Kumar Borah
Signed-off-by: Chaitanya Kumar Borah
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_color.c| 86 +++
drivers/gpu/drm/i915/display/intel_color.h| 1 +
.../drm/i915/display/skl_univ
From: Chaitanya Kumar Borah
This is an example of how vendor specific color operation could be
supported by the uapi
Co-developed-by: Uma Shankar
Signed-off-by: Uma Shankar
Signed-off-by: Chaitanya Kumar Borah
---
drivers/gpu/drm/i915/display/intel_color.c| 42 ---
driver
Add macros to define Plane Post CSC registers
Co-developed-by: Chaitanya Kumar Borah
Signed-off-by: Chaitanya Kumar Borah
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_reg.h | 73 +
1 file changed, 73 insertions(+)
diff --git a/drivers/gpu/drm/i915/i
Extract the LUT and program plane pre-csc registers.
Co-developed-by: Chaitanya Kumar Borah
Signed-off-by: Chaitanya Kumar Borah
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_color.c | 120 +
drivers/gpu/drm/i915/i915_reg.h| 1 +
2 files ch
Register color callbacks for ADL and beyond. While we have to register
new callbacks for pre-blending color operations, re-use callbacks for
post-blend operations.
Co-developed-by: Chaitanya Kumar Borah
Signed-off-by: Chaitanya Kumar Borah
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/di
Extended glk_plane_color_ctl to have plane color checks. This helps
enabling the csc, degamma or gamma block based on user inputs.
Co-developed-by: Chaitanya Kumar Borah
Signed-off-by: Chaitanya Kumar Borah
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/display/skl_universal_plane.c | 13
Add callbacks for color plane operations.
load_plane_luts: used to load pre/post csc luts
load_plane_csc_matrix: used to load csc matrix
Co-developed-by: Chaitanya Kumar Borah
Signed-off-by: Chaitanya Kumar Borah
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_color.c | 6 ++
Extract the LUT and program plane post csc registers.
Co-developed-by: Chaitanya Kumar Borah
Signed-off-by: Chaitanya Kumar Borah
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_color.c | 95 +-
1 file changed, 94 insertions(+), 1 deletion(-)
diff --git a
Add macros to define Plane Degamma registers
Co-developed-by: Chaitanya Kumar Borah
Signed-off-by: Chaitanya Kumar Borah
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_reg.h | 49 +
1 file changed, 49 insertions(+)
diff --git a/drivers/gpu/drm/i915/i9
Load plane color luts as part of atomic plane updates.
This will be done only if the plane color luts are changed.
Co-developed-by: Chaitanya Kumar Borah
Signed-off-by: Chaitanya Kumar Borah
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_color.c | 8
drivers
From: Chaitanya Kumar Borah
Create and attach "SET_COLOR_PIPELINE" property to planes.
Co-developed-by: Uma Shankar
Signed-off-by: Uma Shankar
Signed-off-by: Chaitanya Kumar Borah
---
drivers/gpu/drm/i915/display/intel_color.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gp
From: Chaitanya Kumar Borah
Add supported plane color pipelines. To represent all
hardware blocks in their inactive state, we introduce a pipeline
called "no color pipeline" which is the default pipeline.
Add respective color pipelines for SDR and HDR planes. Create and
attach plane enum property
From: Chaitanya Kumar Borah
Add LUT ranges for color blocks in SDR planes. Userspace can
parse through this information to generate proper LUT data for
respective hardware blocks. It will be exposed to the user space
by the color pipeline.
Co-developed-by: Uma Shankar
Signed-off-by: Uma Shankar
From: Chaitanya Kumar Borah
Create a helper function to add details about LUT ranges that HDR
planes can support. Userspace can parse through this information
to generate proper LUT data for respective hardware blocks. It will
be exposed to the user space by the color pipeline.
Co-developed-by:
SDR planes provides programmable color hardware blocks for
Pre-CSC and Post-CSC operations. Add a color pipeline to
expose these capabilities.
Co-developed-by: Chaitanya Kumar Borah
Signed-off-by: Chaitanya Kumar Borah
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_color.c |
Add color pipeline for HDR planes. It consists of the following
hardware blocks.
* Pre-CSC : This block can used to linearize the input frame buffer data.
The linear data then can be further acted on by the following
color hardware blocks in the display hardware pipeline
Add lut range information for SDR planes. This is used to
hint the userspace what kind of LUT values are needed by
the hardware block. Pre-CSC and Post-CSC blocks have similar
lut range for HDR planes.
Co-developed-by: Chaitanya Kumar Borah
Signed-off-by: Chaitanya Kumar Borah
Signed-off-by: Uma
Add lut range information for HDR planes. This is used to
hint the userspace what kind of LUT values are needed by
the hardware block. Pre-CSC and Post-CSC blocks have
different lut ranges for HDR planes.
Co-developed-by: Chaitanya Kumar Borah
Signed-off-by: Chaitanya Kumar Borah
Signed-off-by:
From: Chaitanya Kumar Borah
Replace the color operation blobs depending on the values sent by
userspace.
Co-developed-by: Uma Shankar
Signed-off-by: Uma Shankar
Signed-off-by: Chaitanya Kumar Borah
---
drivers/gpu/drm/drm_atomic_uapi.c | 97 +++
1 file changed, 97
From: Chaitanya Kumar Borah
When a pipeline switch is requested by user, driver resets
blobs for all the hardware blocks to get to clean state. These
are then populated with the new blob id's as programmed by user.
For the already enabled hardware blocks, if the user does not
add entry in the new
From: Chaitanya Kumar Borah
User can disable the color pipeline entirely, thereby
disabling all the color hardware blocks in the pipeline.
User should set NULL as the blob id and invoke SET_COLOR_PIPELINE
property. Driver will disable all the color hardware blocks by
updating respective blob id'
From: Chaitanya Kumar Borah
This patch manages the references for color blobs.
Co-developed-by: Uma Shankar
Signed-off-by: Uma Shankar
Signed-off-by: Chaitanya Kumar Borah
---
drivers/gpu/drm/drm_atomic_state_helper.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/dr
Add a new structure drm_plane_color to plane state. It consists
of blobs with data needed for respective color HW blocks.
Currently defining below blobs
pre-csc: can be used to linearize the input frame buffer data.
csc: used for color space conversion.
post-csc: can be used non-linearize
Add color lut range structure which is to be used to advertize
the capabilities of pre-csc/post-csc color operation blocks.
Co-developed-by: Chaitanya Kumar Borah
Signed-off-by: Chaitanya Kumar Borah
Signed-off-by: Uma Shankar
---
include/uapi/drm/drm_mode.h | 77 ++
Existing LUT precision structure is having only 16 bit
precision. This is not enough for upcoming enhanced hardwares
and advance usecases like HDR processing. Hence added a new
structure with 32 bit precision values.
Co-developed-by: Chaitanya Kumar Borah
Signed-off-by: Chaitanya Kumar Borah
Sig
Add a new plane blob property "SET_COLOR_PIPELINE" using
which the user can select a color pipeline and send data
for corresponding hardware blocks.
Once the user space decides on a color pipeline, it can
set the pipeline and corresponding data for the hardware
blocks within the pipeline.
Co-deve
Add structures using which user space can set a color pipeline it
desires. The patch introduces two structures
struct drm_color_op_data represents data to be passed
onto individual color hardware blocks.
struct drm_color_pipeline represents the aggregate of drm_color_op_data
structures to program
From: Chaitanya Kumar Borah
Create a helper function to add a color pipeline for a plane.
Color pipeline is an array of struct drm_color_op which represent
a possible logical combination of color operations. Color
operations can be re-arranged, substracted or added to create
distinct color pipeli
From: Chaitanya Kumar Borah
Each hardware plane can consist of multiple color hardware blocks.
These hardware blocks are defined by a color pipeline. In case,
hardware blocks can be re-arranged/muxed a distinct pipeline can
be defined to represent the same.
Introduce a new enum plane property "G
From: Chaitanya Kumar Borah
Each Color Hardware block will be represented uniquely
in the color pipeline. Define the structure to represent
the same.
These color operations will form the building blocks of
a color pipeline which best represents the underlying
Hardware. Color operations can be re
Add the documentation for the new proposed Plane Color Pipeline.
Co-developed-by: Chaitanya Kumar Borah
Signed-off-by: Chaitanya Kumar Borah
Signed-off-by: Uma Shankar
---
.../gpu/rfc/plane_color_pipeline.rst | 394 ++
1 file changed, 394 insertions(+)
create mode 100
Introduction
Modern hardwares have various color processing capabilities both
at pre-blending and post-blending phases in the color pipeline.
The current drm implementation exposes only the post-blending
color hardware blocks. Support for pre-blending hardware is missing.
There are mu
On Mon, Aug 28, 2023 at 05:05:06PM -0700, Jessica Zhang wrote:
> Some drivers support hardware that have optimizations for solid fill
> planes. This series aims to expose these capabilities to userspace as
> some compositors have a solid fill flag (ex. SOLID_COLOR in the Android
> hardware composer
On Mon, Aug 28, 2023 at 05:05:08PM -0700, Jessica Zhang wrote:
> Document and add support for solid_fill property to drm_plane. In
> addition, add support for setting and getting the values for solid_fill.
>
> To enable solid fill planes, userspace must assign a property blob to
> the "solid_fill"
On Mon, 28 Aug 2023 17:05:13 -0700
Jessica Zhang wrote:
> Loosen the requirements for atomic and legacy commit so that, in cases
> where pixel_source != FB, the commit can still go through.
>
> This includes adding framebuffer NULL checks in other areas to account for
> FB being NULL when non-FB
On Mon, 28 Aug 2023 17:05:11 -0700
Jessica Zhang wrote:
> Add solid_fill property data to the atomic plane state dump.
>
> Signed-off-by: Jessica Zhang
> ---
> drivers/gpu/drm/drm_atomic.c | 4
> drivers/gpu/drm/drm_plane.c | 8
> include/drm/drm_plane.h | 3 +++
> 3 files
On Mon, 28 Aug 2023 17:05:09 -0700
Jessica Zhang wrote:
> Add "SOLID_FILL" as a valid pixel source. If the pixel_source property is
> set to "SOLID_FILL", it will display data from the drm_plane "solid_fill"
> blob property.
>
> Reviewed-by: Dmitry Baryshkov
> Signed-off-by: Jessica Zhang
> --
On Mon, 28 Aug 2023 17:05:08 -0700
Jessica Zhang wrote:
> Document and add support for solid_fill property to drm_plane. In
> addition, add support for setting and getting the values for solid_fill.
>
> To enable solid fill planes, userspace must assign a property blob to
> the "solid_fill" plan
On Mon, 28 Aug 2023 17:05:07 -0700
Jessica Zhang wrote:
> Add support for pixel_source property to drm_plane and related
> documentation. In addition, force pixel_source to
> DRM_PLANE_PIXEL_SOURCE_FB in DRM_IOCTL_MODE_SETPLANE as to not break
> legacy userspace.
>
> This enum property will allo
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