Hello Arturo,
On 15/10/2018 15:25, Arturo Perez Garcia wrote:
Hi.
During the last year, we developed a BSP for the r5 processors of the
zcu102 board. We have tested it extensively on HW. The BSP has been
developed to run RTEMS in the R5 processors in lockstep mode, hence it
runs on a single
Hi.
During the last year, we developed a BSP for the r5 processors of the
zcu102 board. We have tested it extensively on HW. The BSP has been
developed to run RTEMS in the R5 processors in lockstep mode, hence it
runs on a single CPU and it doesn't admit SMP. It has been created for
the last
Hi Jan,
RTEMS master currently supports ARM Xilinx Zynq:
https://github.com/RTEMS/rtems/tree/master/bsps/arm/xilinx-zynq.
Please have a look at
https://docs.rtems.org/branches/master/cpu-supplement/arm.html.
To understand the BSP framework, refer to
https://docs.rtems.org/branches/master/bsp-howt
Hello,
we will have access to a Xilinx Zynq ultrascale+ soon.
It has 4xA53 cores.
If I understand it correctly they are based on AArch64 which is currently not
supported by RTEMS.
However, running the processors in 32bit mode would be sufficient.
I have some problems determining what is already
