Re: why must POSIX_Init() call exit() rather than use a "return" statement?

2019-05-06 Thread Sebastian Huber
On 07/05/2019 00:07, Morgan, Keith S wrote: I have noticed that if I do not call exit() in the POSIX_Init() function, RTEMS executables will hang. Why must I call exit() to exit the POSIX_Init() function rather than conclude with a “return” statement? Calling exit() and returning from a PO

Re: RTEMS_FATAL_SOURCE_EXCEPTION in RTEMS

2019-05-06 Thread Chris Johns
On 6/5/19 5:30 pm, Amarnath MB wrote: >> On 3/5/19 7:04 pm, Christian Mauderer wrote: >> > It's still odd why the PC was on some flash address. >> Yes. The SR (below) is `CPSR = 0x20d2`. The mode is 0x12 which is >> IRQ mode and both the I and F bits are set which means interrupts are >> masked

why must POSIX_Init() call exit() rather than use a "return" statement?

2019-05-06 Thread Morgan, Keith S
I have noticed that if I do not call exit() in the POSIX_Init() function, RTEMS executables will hang. Why must I call exit() to exit the POSIX_Init() function rather than conclude with a "return" statement? Take for example, the psx_example3 example application in the examples-v2 repository. T

Re: rtems_binary_semaphore_post from IRQ handler

2019-05-06 Thread Ярослав Лещинский
Hello again, >>Maybe >>this is related to an interrupt with a too high priority, see also: >>https://lists.rtems.org/pipermail/users/2019-April/033102.html I have played around with priorities but no luck. >>What type of fatal error are you seeing? *** FATAL *** fatal source: 9 (RTEMS_FATAL_SO

how to debug _Scheduler_priority_Ready_queue_first

2019-05-06 Thread Jython
assertion "first != _Chain_Tail( &ready_queues[ index ] )" failed: file "../../cpukit/../../../stm32f4/lib/include/rtems/score/schedulerpriorityimpl.h", line 166, function: _Scheduler_priority_Ready_queue_first ___ users mailing list users@rtems.org http:

Re: RTEMS_FATAL_SOURCE_EXCEPTION in RTEMS

2019-05-06 Thread Amarnath MB
Hi Chris, > On 3/5/19 7:04 pm, Christian Mauderer wrote: > > It's still odd why the PC was on some flash address. > > Yes. The SR (below) is `CPSR = 0x20d2`. The mode is 0x12 which is > IRQ mode and both the I and F bits are set which means interrupts are > masked. I feel the CPSR is in this s