Re: Cache routines working with a processor set?

On 2018-12-21 15:06, Sebastian Huber wrote: Hello Daniel, On 21/12/2018 14:55, Daniel Hellstrom wrote: I missed to respond to this email.. It is not currently used by our drivers currently, I think the original use case here is when L3/L2/L1-cache is not updated after DMA. For example, the

Re: Cache routines working with a processor set?

Hello Daniel, On 21/12/2018 14:55, Daniel Hellstrom wrote: I missed to respond to this email.. It is not currently used by our drivers currently, I think the original use case here is when L3/L2/L1-cache is not updated after DMA. For example, the GR740 can be configured to make DMA directly

Re: Cache routines working with a processor set?

Hi Sebastian, I missed to respond to this email.. It is not currently used by our drivers currently, I think the original use case here is when L3/L2/L1-cache is not updated after DMA. For example, the GR740 can be configured to make DMA directly to SDRAM memory, "behind" the L2-cache. In thi

Re: Using AMP in Rtems 4.10, issues using global message queues

thanks!, we will continue working on this. El vie., 14 de dic. de 2018 a la(s) 03:31, Sebastian Huber ( sebastian.hu...@embedded-brains.de) escribió: > Hello Diego, > > On 13/12/2018 13:31, Diego Mercado wrote: > > Hello, > > I am using AMP in Rtems 4.10 and using message queues to share data >