On Thu, May 02, 2013 at 10:58:54AM -0400, MF Nowlan wrote:
> Hi all,
>
> I am working on integrating uTCP and uTLS (
> http://arxiv.org/abs/1103.0463) into Tor to see if we can lower the
> latency due to head of line blocking across circuits. This is
> Tracker Item #7679 (
> https://trac.torprojec
On Sat, May 04, 2013 at 12:13:09PM -0400, MF Nowlan wrote:
> What you're saying about HOL blocking in the output queue for a relay makes
> sense if the receive window fills up, but I didn't explain how uTCP actually
> works. uTCP (and paired with uTLS) is a kernel patch that will expose to the
>
Yes, the initial plan is to maintain ordering within a circuit. Although, even
this is not strictly necessary if the application wishes to handle out of order
packets. For example, a web server could theoretically handle requests for
different resources in any order. But that's a different story
On Thu, May 02, 2013 at 10:58:54AM -0400, MF Nowlan wrote:
> I am working on integrating uTCP and uTLS (
> http://arxiv.org/abs/1103.0463) into Tor to see if we can lower the
> latency due to head of line blocking across circuits.
You have to be careful to preserve cell ordering *within* circuits,
Hi all,
I am working on integrating uTCP and uTLS (
http://arxiv.org/abs/1103.0463) into Tor to see if we can lower the
latency due to head of line blocking across circuits. This is Tracker
Item #7679 ( https://trac.torproject.org/projects/tor/ticket/7679). I
want to first test the Tor code's
