Re: memory barriers and atomic instructions

2017-05-27 Thread Martin Pieuchot
On 23/05/17(Tue) 17:41, Mark Kettenis wrote: > So here is a diff that implements what I proposed recently. This > recognizes that atomic instructions on amd64 already include an > implicit memory barrier and allows us to write optimized code that > avoids a redundant memory barrier. > > Note that

Re: memory barriers and atomic instructions

2017-05-23 Thread Mark Kettenis
> Date: Tue, 23 May 2017 17:58:56 +0200 > From: Mike Belopuhov > > On Tue, May 23, 2017 at 17:41 +0200, Mark Kettenis wrote: > > So here is a diff that implements what I proposed recently. This > > recognizes that atomic instructions on amd64 already include an > > implicit memory barrier and al

Re: memory barriers and atomic instructions

2017-05-23 Thread Mike Belopuhov
On Tue, May 23, 2017 at 17:41 +0200, Mark Kettenis wrote: > So here is a diff that implements what I proposed recently. This > recognizes that atomic instructions on amd64 already include an > implicit memory barrier and allows us to write optimized code that > avoids a redundant memory barrier. >

memory barriers and atomic instructions

2017-05-23 Thread Mark Kettenis
So here is a diff that implements what I proposed recently. This recognizes that atomic instructions on amd64 already include an implicit memory barrier and allows us to write optimized code that avoids a redundant memory barrier. Note that I don't have a use-case for membar_exit_before_atomic()