> Date: Sat, 26 Jun 2021 11:24:57 +
> From: Visa Hankala
>
> On Fri, Jun 25, 2021 at 04:15:43PM +0200, Mark Kettenis wrote:
> > > Date: Fri, 25 Jun 2021 13:27:28 +
> > > From: Visa Hankala
> > >
> > > On Thu, Jun 24, 2021 at 07:02:11PM +, Mickael Torres wrote:
> > > > Hello,
> > > >
On Fri, Jun 25, 2021 at 04:15:43PM +0200, Mark Kettenis wrote:
> > Date: Fri, 25 Jun 2021 13:27:28 +
> > From: Visa Hankala
> >
> > On Thu, Jun 24, 2021 at 07:02:11PM +, Mickael Torres wrote:
> > > Hello,
> > >
> > > On the risc-v SiFive Unmatched the internal cad0 ethernet interface sto
Mark Kettenis wrote:
> > I am surprised that this has not been raised before. I also wonder if
> > riscv64's DMA constraints are fully sane.
>
> There is no DMA constraint on riscv64 yet. We try to avoid having
> such a constraint on platforms that don't have a long history, hoping
> those plat
> Date: Fri, 25 Jun 2021 13:27:28 +
> From: Visa Hankala
>
> On Thu, Jun 24, 2021 at 07:02:11PM +, Mickael Torres wrote:
> > Hello,
> >
> > On the risc-v SiFive Unmatched the internal cad0 ethernet interface stops
> > working randomly after some packets are sent/received. It looks like
Visa Hankala wrote:
> On Thu, Jun 24, 2021 at 07:02:11PM +, Mickael Torres wrote:
> > Hello,
> >
> > On the risc-v SiFive Unmatched the internal cad0 ethernet interface stops
> > working randomly after some packets are sent/received. It looks like it's
> > because the bus_dmamap used isn't
On Thu, Jun 24, 2021 at 07:02:11PM +, Mickael Torres wrote:
> Hello,
>
> On the risc-v SiFive Unmatched the internal cad0 ethernet interface stops
> working randomly after some packets are sent/received. It looks like it's
> because the bus_dmamap used isn't restricted to lower than 4GB phys
Hello,
On the risc-v SiFive Unmatched the internal cad0 ethernet interface stops
working randomly after some packets are sent/received. It looks like it's
because the bus_dmamap used isn't restricted to lower than 4GB physical
addresses, and the interface itself is.
Configuring the interface f
