> Date: Tue, 27 Apr 2021 13:34:01 +
> From: Visa Hankala
>
> On Mon, Apr 26, 2021 at 05:25:18PM +0200, Mark Kettenis wrote:
> > > Date: Mon, 26 Apr 2021 14:19:38 +
> > > From: Visa Hankala
> > >
> > > The following diff adds a preliminary driver for the system-level
> > > control regist
On Mon, Apr 26, 2021 at 05:25:18PM +0200, Mark Kettenis wrote:
> > Date: Mon, 26 Apr 2021 14:19:38 +
> > From: Visa Hankala
> >
> > The following diff adds a preliminary driver for the system-level
> > control registers of Xilinx Zynq-7000. It enables system reset. It also
> > adds clock bits
> Date: Mon, 26 Apr 2021 14:19:38 +
> From: Visa Hankala
>
> The following diff adds a preliminary driver for the system-level
> control registers of Xilinx Zynq-7000. It enables system reset. It also
> adds clock bits for use with the SDIO and Gigabit Ethernet controllers.
>
> On some arm64
The following diff adds a preliminary driver for the system-level
control registers of Xilinx Zynq-7000. It enables system reset. It also
adds clock bits for use with the SDIO and Gigabit Ethernet controllers.
On some arm64 and armv7 platforms, there are separate drivers for clocks
and resets. How
