Re: nsd 4.1.16

2017-04-24 Thread Florian Obser
On Fri, Apr 14, 2017 at 07:52:32AM +, Florian Obser wrote: > rc1 is out, running fine here with minimal-responses: yes for some time FYI: Wouter tagged 4.1.16 release this morning. No changes to RC1, so what we have in tree is 4.1.16. -- I'm not entirely sure you are real.

mail.file.c patch

2017-04-24 Thread Edgar Pettijohn
Not sure if this was intentional or not, but here is a patch to remove a "damned if you do, damned if you don't" situation. Thanks, Edgar Index: mail.file.c === RCS file: /cvs/src/usr.sbin/smtpd/mail.file.c,v retrieving revisio

Re: arm quadruple bus space

2017-04-24 Thread Jonathan Gray
On Mon, Apr 24, 2017 at 09:51:31PM +0200, Mark Kettenis wrote: > On armv7 and arm64 we have this dirty hack to be able to use the > com(4) driver on hardware blocks that have the registers spaced > differently than the origional NS8250/16450/16550. One they I'm going > to fix this properly in com(

Re: ARM64: attach CPUs for identification purposes.

2017-04-24 Thread David Gwynne
> On 25 Apr 2017, at 6:18 am, Mark Kettenis wrote: > >> Date: Mon, 24 Apr 2017 16:01:39 -0400 >> From: Dale Rahn >> >> The below code is set up to attach and identify processors for arm64 >> currently it only identifies model, not cache size, but that can be added >> later. It is set up to att

add -msave-args to gcc on amd64

2017-04-24 Thread David Gwynne
i got sick of not having arguments in ddb stack traces on amd64. the lack of them is because the first 6 arguments are generally passed in registers, not on the stack. recovering the arguments seems to rely on dwarf, which is complicated, which is not something i think is right for ddb. solaris ha

Re: ARM64: attach CPUs for identification purposes.

2017-04-24 Thread Dale Rahn
On Mon, Apr 24, 2017 at 10:18:08PM +0200, Mark Kettenis wrote: > > Date: Mon, 24 Apr 2017 16:01:39 -0400 > > From: Dale Rahn > > > > The below code is set up to attach and identify processors for arm64 > > currently it only identifies model, not cache size, but that can be added > > later. It is

Re: arm quadruple bus space

2017-04-24 Thread aa e30
24.4.2017 22.54 "Mark Kettenis" kirjoitti: On armv7 and arm64 we have this dirty hack to be able to use the com(4) driver on hardware blocks that have the registers spaced differently than the origional NS8250/16450/16550. One they I'm going to fix this properly in com(4) itself, but not today.

Re: ARM64: attach CPUs for identification purposes.

2017-04-24 Thread Mark Kettenis
> Date: Mon, 24 Apr 2017 16:01:39 -0400 > From: Dale Rahn > > The below code is set up to attach and identify processors for arm64 > currently it only identifies model, not cache size, but that can be added > later. It is set up to attach secondary processors later (for when SMP > is present). I

ARM64: attach CPUs for identification purposes.

2017-04-24 Thread Dale Rahn
The below code is set up to attach and identify processors for arm64 currently it only identifies model, not cache size, but that can be added later. It is set up to attach secondary processors later (for when SMP is present). diff --git a/sys/arch/arm64/arm64/cpu.c b/sys/arch/arm64/arm64/cpu.c ne

arm quadruple bus space

2017-04-24 Thread Mark Kettenis
On armv7 and arm64 we have this dirty hack to be able to use the com(4) driver on hardware blocks that have the registers spaced differently than the origional NS8250/16450/16550. One they I'm going to fix this properly in com(4) itself, but not today. Now on the Rockchip RK3288, the Synopsis Des

Re: [PATCH 01/04] Constant time AES implementation

2017-04-24 Thread Mike Belopuhov
On Mon, Apr 24, 2017 at 04:36 +0200, Mike Belopuhov wrote: > Hi, > > This is the first diff in series to replace our table-driven AES > implementation in the crypto framework with a constant time one > authored by Thomas Pornin. I've been on the lookout for a complete > constant time implementati

Re: Add Cortex-A12 support

2017-04-24 Thread Patrick Wildt
On Mon, Apr 24, 2017 at 06:48:22PM +0200, Mark Kettenis wrote: > Even though ARM "merged" the Cortex-A12 as Cortex-A17, there are cores > with the original Cortex-A12 MIDR out there. So it is useful to > differentiate between them. The Rockchip RK3288 has 4 of these cores. > The diff below adds s

Add Cortex-A12 support

2017-04-24 Thread Mark Kettenis
Even though ARM "merged" the Cortex-A12 as Cortex-A17, there are cores with the original Cortex-A12 MIDR out there. So it is useful to differentiate between them. The Rockchip RK3288 has 4 of these cores. The diff below adds support for these cores. As a teaser, here s a dmesg for the Asus Tinke

Re: PATCH: change tiling behaviour in cwm(1)

2017-04-24 Thread Antoine Jacoutot
On April 24, 2017 2:19:31 PM GMT+02:00, Okan Demirmen wrote: >On Wed 2017.04.12 at 10:38 +0200, Antoine Jacoutot wrote: >> On Tue, Apr 11, 2017 at 06:00:21PM +0200, Gerrit Meyerheim wrote: >> > Hi @tech, >> > >> > The way cwm(1) currently implements tiling (off by default) is >> > corresponding t

Re: PATCH: change tiling behaviour in cwm(1)

2017-04-24 Thread Okan Demirmen
On Wed 2017.04.12 at 10:38 +0200, Antoine Jacoutot wrote: > On Tue, Apr 11, 2017 at 06:00:21PM +0200, Gerrit Meyerheim wrote: > > Hi @tech, > > > > The way cwm(1) currently implements tiling (off by default) is > > corresponding to this for vtile, > > > > - > > |

Re: [PATCH 02/04] Adjust AES testcase to the new implementation

2017-04-24 Thread Damien Miller
ok On Mon, 24 Apr 2017, Mike Belopuhov wrote: > Adjusts the regress test. > > --- > regress/sys/crypto/aes/Makefile | 2 +- > regress/sys/crypto/aes/aestest.c | 10 +- > 2 files changed, 6 insertions(+), 6 deletions(-) > > diff --git regress/sys/crypto/aes/Makefile regress/sys/crypto