Parts of this were stolen from kettenis.
Hey, wouldn't it be cool if static PIE executables took advantage of the
RELRO information too?
Philip
Index: lib/csu/boot.h
===
RCS file: /cvs/src/lib/csu/boot.h,v
retrieving revision 1.
Ahem.
What I mean is that with some patching, RELRO can be enabled by default on
several archs. The first chunk below enables it on x86, arm, and sparc64.
I'm 95% positive that it would Just Work on alpha and sh (TEXT_PLT archs
like amd64, arm, and i386) and sparc (looks like sparc64, shock!
We have kbind(2), so we can do RELRO process *ALWAYS*, and not just when
-znow is used to perform all relocations at load-time.
So, teach ld to just test for -zrelro.
ok?
Philip
Index: gnu/usr.bin/binutils-2.17/ld/genscripts.sh
=
On Sun, 7 Aug 2016, Theo Buehler wrote:
> The getentropy_*.c headers contain outdated links to the getentropy(2)
> manual.
>
> ok?
ok guenther@
powerpc has two models of GOT+PLT placement: secure PLT (the new default)
and BSS PLT. ld handles the two possibilities in linker scripts by
including both locations in the script, but putting a constraint "SPECIAL"
on them, ala:
.plt: SPECIAL { *(.plt) }
As part of my RELRO hac
The getentropy_*.c headers contain outdated links to the getentropy(2)
manual.
ok?
Index: getentropy_aix.c
===
RCS file: /var/cvs/src/lib/libcrypto/crypto/getentropy_aix.c,v
retrieving revision 1.4
diff -u -p -r1.4 getentropy_aix.c
-
Having fixed the other archs, arm's now the last arch that doesn't pass
&_DYNAMIC to _dl_boot_bind(). This is the diff I'm running with, moving
up the calculation of &_GLOBAL_OFFSET_TABLE_ slightly and then using
_DYNAMIC(GOTOFF) to get the address we want from there. Is there a better
way,
On Sun, Aug 07, 2016 at 10:54:00AM +1000, Jonathan Matthew wrote:
> As I noted when I added the driver, ure(4) currently doesn't work after a
> reboot, because the device needs to be reset before it can be probed again.
> I don't know enough about usb (or this particular hardware) to understand why
Let's teach ld.so to look for a PT_GNU_RELRO section per object and, if
present, mprotect(PROT_READ) the range it covers *instead of* the
__got_start .. __got_end range.
Two interesting bits are in here:
1) we need to move up the handling of DT_DEBUG to before relocation is
done, so that
As I noted when I added the driver, ure(4) currently doesn't work after a
reboot, because the device needs to be reset before it can be probed again.
I don't know enough about usb (or this particular hardware) to understand why
this is, but I can at least work out how to do it.
My current approach
On Sat, Aug 06, 2016 at 12:02:53PM +0200, Mark Kettenis wrote:
> I'd appreciate it if somebody could test this on a system with a
> Cortex-A8 processor.
Before this patch, it used to take around 58 min to build kernel on
BeagleBone Black here. It's now taking around 23 min.
--
db
This adds xor cookies to the arm setjmp family.
To make the register jockeying easier, it rearranges the order of the
registers in the jmpbuf, moving up the (cookied) sp and lr registers to
before r4-r11, and then completely leaving out r12, as it's not
callee-saved in the ABI. Thus the first
> On 22/06/16(Wed) 00:53, Lampshade wrote:
> > I don't know if this is enough, but I haven't had access to web
> > using other device when kernel panicked.
>
> What's the output of ifconfig and route -n show for this system?
>
Sorry for silence.
Kernel panic happened only once in June and this
On Sat, Aug 06, 2016 at 12:02:53PM +0200, Mark Kettenis wrote:
> The diff below puts the page tables on armv7 in cachable memory. This
> should speed things up a little bit, especially on processors that
> walk the page tables coherently, which is pretty much all of them
> except for Cortex-A8.
jot.c has a loop containing a 16-way switch that fiddles with hardcoded
values:
while (mask)/* 4 bit mask has 1's where last 4 args were given */
switch (mask) { /* fill in the 0's by default or computation */
case 001:
reps = REP
> Date: Thu, 4 Aug 2016 13:47:36 +0200
> From: Marcus Glocker
>
> On Wed, Aug 03, 2016 at 03:33:21PM -0600, Theo de Raadt wrote:
>
> > > I don't think the com(4) part of the diff is quite right. This busy
> > > indicator feature seems to be specific to the Designware core. I
> > > can't find t
The diff below puts the page tables on armv7 in cachable memory. This
should speed things up a little bit, especially on processors that
walk the page tables coherently, which is pretty much all of them
except for Cortex-A8. We check whether the page table walk is
coherent by checking the aprprop
> Date: Sat, 6 Aug 2016 04:26:27 -0400
> From: Ian Sutton
Hi Ian,
> amdisplay(4) drives the LCD controller in am335x SoCs (beaglebone black
> for us). Patch is unfinished but is further along than imxdisplay(4).
> (imx6q's display subsystem is enormously complicated and poorly
> documented; I in
amdisplay(4) drives the LCD controller in am335x SoCs (beaglebone black
for us). Patch is unfinished but is further along than imxdisplay(4).
(imx6q's display subsystem is enormously complicated and poorly
documented; I intend to finish both but am working on this one for now).
Interestingly, the
19 matches
Mail list logo
