[PATCH v4 02/19] intel_iommu: Declare supported PASID size

From: Clement Mathieu--Drif PSS field of the ecap register stores the supported PASID size minus 1. Thus, this commit adds support for 20bits PASIDs. Signed-off-by: Clement Mathieu--Drif --- hw/i386/intel_iommu.c | 2 +- hw/i386/intel_iommu_internal.h | 1 + 2 files changed, 2

[PATCH v4 03/19] memory: Allow to store the PASID in IOMMUTLBEntry

From: Clement Mathieu--Drif This will be useful for devices that support ATS and need to store entries in an ATC (device IOTLB). Signed-off-by: Clement Mathieu--Drif --- include/exec/memory.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/exec/memory.h b/include/exec/memory.h

[PATCH v4 06/19] pcie: Helper functions to check if PASID is enabled

From: Clement Mathieu--Drif pasid_enabled checks whether the capability is present or not. If so, we read the configuration space to get the status of the feature (enabled or not). Signed-off-by: Clement Mathieu--Drif --- hw/pci/pcie.c | 9 + include/hw/pci/pcie.h | 2 ++ 2

Re: [PATCH v4 14/19] atc: Add unit tests

On 14/05/2025 9:36 am, Michael S. Tsirkin wrote: > Caution: External email. Do not open attachments or click links, unless this > email comes from a known sender and you know the content is safe. > > > On Thu, Feb 27, 2025 at 10:54:47AM +, CLEMENT MATHIEU--DRIF wrote: &

Re: [PATCH v5 2/2] intel_iommu: Take locks when looking for and creating address spaces

On 14/05/2025 1:48 pm, Michael S. Tsirkin wrote: > Caution: External email. Do not open attachments or click links, unless this > email comes from a known sender and you know the content is safe. > > > On Wed, Apr 30, 2025 at 12:48:06PM +, CLEMENT MATHIEU--DRIF wrote: >

[PATCH 04/11] pcie: Add a helper to declare the PRI capability for a pcie device

Signed-off-by: Clement Mathieu--Drif --- hw/pci/pcie.c | 26 ++ include/hw/pci/pcie.h | 5 - include/hw/pci/pcie_regs.h | 3 +++ 3 files changed, 33 insertions(+), 1 deletion(-) diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c index 36de709801

[PATCH 00/11] SVM API declaration for emulated devices

- PRI - Device IOTLB invalidations - Requests with already pre-translated addresses - A demo device - A simple driver for the demo device - A userspace program (for testing and demonstration purposes) https://github.com/BullSequana/Qemu-in-guest-SVM-demo Clement Mathi

[PATCH 01/11] pcie: Add helper to declare PASID capability for a pcie device

Signed-off-by: Clement Mathieu--Drif --- hw/pci/pcie.c | 25 + include/hw/pci/pcie.h | 6 +- include/hw/pci/pcie_regs.h | 5 + 3 files changed, 35 insertions(+), 1 deletion(-) diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c index 1b12db6fa2

[PATCH 09/11] pci: Add a pci-level initialization function for IOMMU notifiers

This is meant to be used by ATS-capable devices. Signed-off-by: Clement Mathieu--Drif --- hw/pci/pci.c | 17 + include/hw/pci/pci.h | 33 + 2 files changed, 50 insertions(+) diff --git a/hw/pci/pci.c b/hw/pci/pci.c index fc4954ac81

[PATCH 08/11] memory: Store user data pointer in the IOMMU notifiers

This will help developers of ATS-capable devices to track a state. Signed-off-by: Clement Mathieu--Drif --- include/system/memory.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/system/memory.h b/include/system/memory.h index fbbf4cf911..fc35a0dcad 100644 --- a/include/system

[PATCH 11/11] pci: Add a PCI-level API for PRI

A device can send a PRI request to the IOMMU using pci_pri_request_page. The PRI response is sent back using the notifier managed with pci_pri_register_notifier and pci_pri_unregister_notifier. Signed-off-by: Clement Mathieu--Drif Co-authored-by: Ethan Milon --- hw/pci/pci.c | 66

[PATCH 03/11] pcie: Helper function to check if ATS is enabled

ats_enabled checks whether the capability is present or not. If so, we read the configuration space to get the status of the feature (enabled or not). Signed-off-by: Clement Mathieu--Drif --- hw/pci/pcie.c | 9 + include/hw/pci/pcie.h | 1 + 2 files changed, 10 insertions

[PATCH 05/11] pcie: Helper functions to check to check if PRI is enabled

pri_enabled can be used to check whether the capability is present and enabled on a PCIe device Signed-off-by: Clement Mathieu--Drif --- hw/pci/pcie.c | 9 + include/hw/pci/pcie.h | 1 + 2 files changed, 10 insertions(+) diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c index

[PATCH 07/11] pci: Add an API to get IOMMU's min page size and virtual address width

This kind of information is needed by devices implementing ATS in order to initialize their translation cache. Signed-off-by: Clement Mathieu--Drif --- hw/pci/pci.c | 17 + include/hw/pci/pci.h | 26 ++ 2 files changed, 43 insertions(+) diff

[PATCH 02/11] pcie: Helper functions to check if PASID is enabled

pasid_enabled checks whether the capability is present or not. If so, we read the configuration space to get the status of the feature (enabled or not). Signed-off-by: Clement Mathieu--Drif --- hw/pci/pcie.c | 9 + include/hw/pci/pcie.h | 2 ++ 2 files changed, 11 insertions

[PATCH 10/11] pci: Add a pci-level API for ATS

Devices implementing ATS can send translation requests using pci_ats_request_translation. The invalidation events are sent back to the device using the iommu notifier managed with pci_iommu_register_iotlb_notifier / pci_iommu_unregister_iotlb_notifier. Signed-off-by: Clement Mathieu--Drif Co

[PATCH 06/11] pci: Cache the bus mastering status in the device

The cached is_master value is necessary to know if a device is allowed to issue ATS/PRI requests or not as these operations do not go through the master_enable memory region. Signed-off-by: Clement Mathieu--Drif --- hw/pci/pci.c| 23 +-- include/hw/pci

Re: [PATCH 00/11] SVM API declaration for emulated devices

Just cc'ing riscv team Thanks >cmd On 20/05/2025 9:18 am, CLEMENT MATHIEU--DRIF wrote: > This patch set belongs to a list of series that add SVM support in VT-d. > > Here we focus on introducing a common PCI-level API for ATS and PRI to be > used by virtual devices. >

[PATCH 1/2] pci: Add a memory attribute for pre-translated DMA operations

The address_type bit will be set to PCI_AT_TRANSLATED by devices that use cached addresses obtained via ATS. Signed-off-by: Clement Mathieu--Drif --- include/exec/memattrs.h | 3 +++ include/hw/pci/pci.h| 9 + 2 files changed, 12 insertions(+) diff --git a/include/exec/memattrs.h b

[PATCH 2/2] memory: Add permissions in IOMMUAccessFlags

) : - Execute Requested - Privileged Mode Requested - Global - Untranslated Only IOMMU_ACCESS_FLAG sets the additional flags to 0 Signed-off-by: Clement Mathieu--Drif --- include/system/memory.h | 23 +-- 1 file changed, 21 insertions(+), 2 deletions(-) diff

[PATCH 0/2] Memory and PCI definitions for emulated ATS

- Global - Untranslated Only (cannot be used with 'Address type = translated') Clement Mathieu--Drif (2): pci: Add a memory attribute for pre-translated DMA operations memory: Add permissions in IOMMUAccessFlags include/exec/memattrs.h | 3 +++ include/hw/pci/pci.h| 9 +

Re: [PATCH 0/2] Memory and PCI definitions for emulated ATS

Hi Peter On 20/06/2025 4:35 pm, Peter Xu wrote: > Caution: External email. Do not open attachments or click links, unless this > email comes from a known sender and you know the content is safe. > > > On Fri, Jun 20, 2025 at 05:56:49AM +, CLEMENT MATHIEU--DRIF wrote: >&

Re: [PATCH v1 04/15] intel_iommu: Introduce a new structure VTDHostIOMMUDevice

Hi, On 06/06/2025 12:04 pm, Zhenzhong Duan wrote: > Caution: External email. Do not open attachments or click links, unless this > email comes from a known sender and you know the content is safe. > > > Introduce a new structure VTDHostIOMMUDevice which replaces > HostIOMMUDevice to be stored i

Re: [PATCH 0/2] Memory and PCI definitions for emulated ATS

On 23/06/2025 3:15 pm, Peter Xu wrote: > Caution: External email. Do not open attachments or click links, unless this > email comes from a known sender and you know the content is safe. > > > On Mon, Jun 23, 2025 at 05:43:06AM +, CLEMENT MATHIEU--DRIF wrote: >> Hi

[PATCH 05/10] intel_iommu: Declare supported PASID size

the PSS field of the extended capabilities stores the supported PASID size minus 1. This commit adds support for 8bits PASIDs (limited by MemTxAttrs::pid). Signed-off-by: Clement Mathieu--Drif --- hw/i386/intel_iommu.c | 2 +- hw/i386/intel_iommu_internal.h | 1 + 2 files changed, 2

[PATCH 10/10] intel_iommu: Add support for ATS

Signed-off-by: Clement Mathieu--Drif --- hw/i386/intel_iommu.c | 63 +++ 1 file changed, 63 insertions(+) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 1b1b0b5632..fe9a5f2872 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386

[PATCH 09/10] intel_iommu: Set address mask when a translation fails and adjust W permission

Implements the behavior defined in section 10.2.3.5 of PCIe spec rev 5. This is needed by devices that support ATS. Signed-off-by: Clement Mathieu--Drif --- hw/i386/intel_iommu.c | 12 +--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386

[PATCH 03/10] memory: Allow to store the PASID in IOMMUTLBEntry

This will be useful for devices that support ATS and need to store entries in an ATC (device IOTLB). Signed-off-by: Clement Mathieu--Drif --- include/system/memory.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/system/memory.h b/include/system/memory.h index 1672622d70

[PATCH 01/10] pci: Add a memory attribute for pre-translated DMA operations

The address_type bit will be set to PCI_AT_TRANSLATED by devices that use cached addresses obtained via ATS. Signed-off-by: Clement Mathieu--Drif --- include/exec/memattrs.h | 3 +++ include/hw/pci/pci.h| 9 + 2 files changed, 12 insertions(+) diff --git a/include/exec/memattrs.h b

[PATCH 07/10] intel_iommu: Implement the PCIIOMMUOps callbacks related to invalidations of device-IOTLB

Signed-off-by: Clement Mathieu--Drif --- hw/i386/intel_iommu.c | 35 +++ 1 file changed, 35 insertions(+) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index affa7768e6..234c452849 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c

[PATCH 06/10] intel_iommu: Implement vtd_get_iotlb_info from PCIIOMMUOps

Signed-off-by: Clement Mathieu--Drif --- hw/i386/intel_iommu.c | 10 ++ 1 file changed, 10 insertions(+) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 71497f1936..affa7768e6 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -4733,10 +4733,20 @@ static

[PATCH 08/10] intel_iommu: Return page walk level even when the translation fails

We will use this information in vtd_do_iommu_translate to populate the IOMMUTLBEntry and indicate the correct page mask. This prevents ATS devices from sending many useless translation requests when a megapage or gigapage is not present. Signed-off-by: Clement Mathieu--Drif --- hw/i386

[PATCH v5 00/10] intel_iommu: Add ATS support

ew by Michael: - Split long lines in memory.h - Change patch encoding (no UTF-8) - Changes after review by Zhenzhong: - Rework "Fill the PASID field when creating an IOMMUTLBEntry" Clement Mathieu--Drif (10): pci: Add a memory attribute for pre-translated DMA ope

[PATCH 02/10] memory: Add permissions in IOMMUAccessFlags

) : - Execute Requested - Privileged Mode Requested - Global - Untranslated Only IOMMU_ACCESS_FLAG sets the additional flags to 0 Signed-off-by: Clement Mathieu--Drif --- include/system/memory.h | 23 +-- 1 file changed, 21 insertions(+), 2 deletions(-) diff

[PATCH 04/10] intel_iommu: Fill the PASID field when creating an IOMMUTLBEntry

PASID value must be used by devices as a key (or part of a key) when populating their ATC with the IOTLB entries returned by the IOMMU. Signed-off-by: Clement Mathieu--Drif --- hw/i386/intel_iommu.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/hw/i386/intel_iommu.c b/hw/i386

Re: [PATCH v2] intel_iommu: Allow both Status Write and Interrupt Flag in QI wait

On 14/07/2025 11:22 pm, Konstantin Belousov wrote: > Caution: External email. Do not open attachments or click links, unless this > email comes from a known sender and you know the content is safe. > > > On Mon, Jul 14, 2025 at 05:41:22PM +0100, David Woodhouse wrote: >> On 14 July 2025 15:28:

Re: [PATCH v2] intel_iommu: Allow both Status Write and Interrupt Flag in QI wait

On 15/07/2025 2:35 pm, Yi Liu wrote: > Caution: External email. Do not open attachments or click links, unless > this email comes from a known sender and you know the content is safe. > > > On 2025/7/15 14:11, CLEMENT MATHIEU--DRIF wrote: >> >> >> On 14/07/2

Re: [PATCH v2] intel_iommu: Allow both Status Write and Interrupt Flag in QI wait

On 15/07/2025 10:27 am, David Woodhouse wrote: > On Tue, 2025-07-15 at 06:11 +0000, CLEMENT MATHIEU--DRIF wrote: >> >> >> On 14/07/2025 11:22 pm, Konstantin Belousov wrote: >>> Caution: External email. Do not open attachments or click links, >>> unless t

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