[PATCH v3 0/3] VT-d minor fixes

From: Clément Mathieu--Drif Various fixes for VT-d This series contains fixes that will be necessary when adding in-guest (fully emulated) SVM support. v3 FRCD construction macro : - Longer sha1 for the 'Fixes' tag - Add '.' at the end of the sentence Make types mat

[PATCH v3 1/3] intel_iommu: fix FRCD construction macro.

From: Clément Mathieu--Drif The constant must be unsigned, otherwise the two's complement overrides the other fields when a PASID is present. Fixes: 1b2b12376c8a ("intel-iommu: PASID support") Signed-off-by: Clément Mathieu--Drif Reviewed-by: Yi Liu --- hw/i386/intel_iommu_internal.h | 2 +-

[PATCH v3 2/3] intel_iommu: fix type of the mask field in VTDIOTLBPageInvInfo

From: Clément Mathieu--Drif VTDIOTLBPageInvInfo.mask might not fit in an uint8_t. Moreover, this field is used in binary operations with 64-bit addresses. Signed-off-by: Clément Mathieu--Drif --- hw/i386/intel_iommu_internal.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a

Re: [PATCH v1 0/8] PRI support for VT-d

On 05/07/2024 05:03, Yi Liu wrote: > Caution: External email. Do not open attachments or click links, > unless this email comes from a known sender and you know the content > is safe. > > > On 2024/5/30 20:24, CLEMENT MATHIEU--DRIF wrote: >> This series belongs to a lis

Re: [PATCH v3 3/3] intel_iommu: make types match

On 05/07/2024 10:51, Duan, Zhenzhong wrote: > Caution: External email. Do not open attachments or click links, unless this > email comes from a known sender and you know the content is safe. > > >> -Original Message- >> From: CLEMENT MATHIEU--DRIF >> Subje

Re: [PATCH v3 2/3] intel_iommu: fix type of the mask field in VTDIOTLBPageInvInfo

On 05/07/2024 10:51, Michael S. Tsirkin wrote: Caution: External email. Do not open attachments or click links, unless this email comes from a known sender and you know the content is safe. On Fri, Jul 05, 2024 at 05:03:17AM +, CLEMENT MATHIEU--DRIF wrote: From: Clément Mathieu--Drif

[PATCH v4 3/4] intel_iommu: fix type of the mask field in VTDIOTLBPageInvInfo

From: Clément Mathieu--Drif The mask we are trying to store into VTDIOTLBPageInvInfo.mask might not fit in an uint8_t. Use uint64_t to avoid overflows Signed-off-by: Clément Mathieu--Drif --- hw/i386/intel_iommu_internal.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/

[PATCH v4 1/4] intel_iommu: fix FRCD construction macro

From: Clément Mathieu--Drif The constant must be unsigned, otherwise the two's complement overrides the other fields when a PASID is present. Fixes: 1b2b12376c8a ("intel-iommu: PASID support") Signed-off-by: Clément Mathieu--Drif Reviewed-by: Yi Liu Reviewed-by: Zhenzhong Duan --- hw/i386/i

[PATCH v4 2/4] intel_iommu: move VTD_FRCD_PV and VTD_FRCD_PP declarations

From: Clément Mathieu--Drif These 2 macros are for high 64-bit of the FRCD registers. Declarations have to be moved accordingly. Signed-off-by: Clément Mathieu--Drif --- hw/i386/intel_iommu_internal.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/i386/intel_iommu_i

[PATCH v4 4/4] intel_iommu: make types match

From: Clément Mathieu--Drif The 'level' field in vtd_iotlb_key is an unsigned integer. We don't need to store level as an int in vtd_lookup_iotlb. This is not an issue by itself, but using unsigned here seems cleaner. Signed-off-by: Clément Mathieu--Drif --- hw/i386/intel_iommu.c | 2 +- 1 fi

[PATCH v4 0/4] VT-d minor fixes

From: Clément Mathieu--Drif Various fixes for VT-d This series contains fixes that will be necessary when adding in-guest (fully emulated) SVM support. v4 - Move declarations of VTD_FRCD_PV and VTD_FRCD_PP - intel_iommu: make types match: - edit commit message to explain that we

[PATCH v5 0/4] VT-d minor fixes

From: Clément Mathieu--Drif Various fixes for VT-d This series contains fixes that will be necessary when adding in-guest (fully emulated) SVM support. v5 intel_iommu: fix FRCD construction macro: - Remove empty line after 'Fixes' intel_iommu: fix type of the mask field in

[PATCH v5 1/4] intel_iommu: fix FRCD construction macro

From: Clément Mathieu--Drif The constant must be unsigned, otherwise the two's complement overrides the other fields when a PASID is present. Fixes: 1b2b12376c8a ("intel-iommu: PASID support") Signed-off-by: Clément Mathieu--Drif Reviewed-by: Yi Liu Reviewed-by: Zhenzhong Duan --- hw/i386/in

[PATCH v5 4/4] intel_iommu: make type match

From: Clément Mathieu--Drif The 'level' field in vtd_iotlb_key is an unsigned integer. We don't need to store level as an int in vtd_lookup_iotlb. This is not an issue by itself, but using unsigned here seems cleaner. Signed-off-by: Clément Mathieu--Drif --- hw/i386/intel_iommu.c | 2 +- 1 fi

[PATCH v5 2/4] intel_iommu: move VTD_FRCD_PV and VTD_FRCD_PP declarations

From: Clément Mathieu--Drif These 2 macros are for high 64-bit of the FRCD registers. Declarations have to be moved accordingly. Signed-off-by: Clément Mathieu--Drif --- hw/i386/intel_iommu_internal.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/i386/intel_iommu_i

[PATCH v5 3/4] intel_iommu: fix type of the mask field in VTDIOTLBPageInvInfo

From: Clément Mathieu--Drif The mask we are trying to store into VTDIOTLBPageInvInfo.mask might not fit in an uint8_t. Use uint64_t to avoid overflows. Per the below code, it can overflow as am can be larger than 8 according to the CH 6.5.2.3 IOTLB Invalidate. And you may want a fix tag as well.

Re: [PATCH v2] hw/i386/intel_iommu: Block CFI when necessary

Hi On 08/07/2024 12:08, Yuke Peng wrote: > Caution: External email. Do not open attachments or click links, unless this > email comes from a known sender and you know the content is safe. > > > According to Intel VT-d specification 5.1.4, CFI must be blocked when > Extended Interrupt Mode is enab

[PATCH v6 0/4] VT-d minor fixes

From: Clément Mathieu--Drif Various fixes for VT-d This series contains fixes that will be necessary when adding in-guest (fully emulated) SVM support. v6 intel_iommu: fix type of the mask field in VTDIOTLBPageInvInfo: - Add 'Fixes' tag v5 intel_iommu: fix FRCD construction mac

[PATCH v6 3/4] intel_iommu: fix type of the mask field in VTDIOTLBPageInvInfo

From: Clément Mathieu--Drif The mask we are trying to store into VTDIOTLBPageInvInfo.mask might not fit in an uint8_t. Use uint64_t to avoid overflows. Per the below code, it can overflow as am can be larger than 8 according to the CH 6.5.2.3 IOTLB Invalidate. And you may want a fix tag as well.

[PATCH v6 2/4] intel_iommu: move VTD_FRCD_PV and VTD_FRCD_PP declarations

From: Clément Mathieu--Drif These 2 macros are for high 64-bit of the FRCD registers. Declarations have to be moved accordingly. Signed-off-by: Clément Mathieu--Drif Reviewed-by: Minwoo Im --- hw/i386/intel_iommu_internal.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git

[PATCH v6 1/4] intel_iommu: fix FRCD construction macro

From: Clément Mathieu--Drif The constant must be unsigned, otherwise the two's complement overrides the other fields when a PASID is present. Fixes: 1b2b12376c8a ("intel-iommu: PASID support") Signed-off-by: Clément Mathieu--Drif Reviewed-by: Yi Liu Reviewed-by: Zhenzhong Duan Reviewed-by: Mi

[PATCH v6 4/4] intel_iommu: make type match

From: Clément Mathieu--Drif The 'level' field in vtd_iotlb_key is an unsigned integer. We don't need to store level as an int in vtd_lookup_iotlb. This is not an issue by itself, but using unsigned here seems cleaner. Signed-off-by: Clément Mathieu--Drif Reviewed-by: Yi Liu --- hw/i386/intel

Re: [PATCH ats_vtd v5 20/22] pci: add a pci-level API for ATS

On 09/07/2024 12:15, Minwoo Im wrote: > Caution: External email. Do not open attachments or click links, unless this > email comes from a known sender and you know the content is safe. > > > On 24-07-02 05:52:45, CLEMENT MATHIEU--DRIF wrote: >> From: Clément Mathieu

Re: [PATCH v6 3/4] intel_iommu: fix type of the mask field in VTDIOTLBPageInvInfo

On 09/07/2024 16:01, Yi Liu wrote: > Caution: External email. Do not open attachments or click links, > unless this email comes from a known sender and you know the content > is safe. > > > On 2024/7/9 14:18, CLEMENT MATHIEU--DRIF wrote: >> From: Clément Mathieu--Dri

[PATCH v7 1/4] intel_iommu: fix FRCD construction macro

From: Clément Mathieu--Drif The constant must be unsigned, otherwise the two's complement overrides the other fields when a PASID is present. Fixes: 1b2b12376c8a ("intel-iommu: PASID support") Signed-off-by: Clément Mathieu--Drif Reviewed-by: Yi Liu Reviewed-by: Zhenzhong Duan Reviewed-by: Mi

[PATCH v7 0/4] VT-d minor fixes

From: Clément Mathieu--Drif Various fixes for VT-d This series contains fixes that will be necessary when adding in-guest (fully emulated) SVM support. v7 intel_iommu: fix type of the mask field in VTDIOTLBPageInvInfo: - Edit commit message v6 intel_iommu: fix type of the mask

[PATCH v7 2/4] intel_iommu: move VTD_FRCD_PV and VTD_FRCD_PP declarations

From: Clément Mathieu--Drif These 2 macros are for high 64-bit of the FRCD registers. Declarations have to be moved accordingly. Signed-off-by: Clément Mathieu--Drif Reviewed-by: Minwoo Im Reviewed-by: Yi Liu --- hw/i386/intel_iommu_internal.h | 4 ++-- 1 file changed, 2 insertions(+), 2 del

[PATCH v7 3/4] intel_iommu: fix type of the mask field in VTDIOTLBPageInvInfo

From: Clément Mathieu--Drif Per the below code, it can overflow as am can be larger than 8 according to the CH 6.5.2.3 IOTLB Invalidate. Use uint64_t to avoid overflows. Fixes: b5a280c00840 ("intel-iommu: add IOTLB using hash table") Signed-off-by: Clément Mathieu--Drif Reviewed-by: Minwoo Im

[PATCH v7 4/4] intel_iommu: make type match

From: Clément Mathieu--Drif The 'level' field in vtd_iotlb_key is an unsigned integer. We don't need to store level as an int in vtd_lookup_iotlb. This is not an issue by itself, but using unsigned here seems cleaner. Signed-off-by: Clément Mathieu--Drif Reviewed-by: Yi Liu --- hw/i386/intel

Re: [PATCH v6 3/4] intel_iommu: fix type of the mask field in VTDIOTLBPageInvInfo

On 09/07/2024 16:01, Yi Liu wrote: > Caution: External email. Do not open attachments or click links, > unless this email comes from a known sender and you know the content > is safe. > > > On 2024/7/9 14:18, CLEMENT MATHIEU--DRIF wrote: >> From: Clément Mathieu--Dri

Re: [PATCH ats_vtd v5 20/22] pci: add a pci-level API for ATS

On 09/07/2024 23:17, Minwoo Im wrote: > Caution: External email. Do not open attachments or click links, unless this > email comes from a known sender and you know the content is safe. > > > On 24-07-09 11:58:53, CLEMENT MATHIEU--DRIF wrote: >> >> On 09/07/

Re: [PATCH ats_vtd v5 20/22] pci: add a pci-level API for ATS

On 11/07/2024 10:04, Minwoo Im wrote: > Caution: External email. Do not open attachments or click links, unless this > email comes from a known sender and you know the content is safe. > > > On 24-07-10 05:17:42, CLEMENT MATHIEU--DRIF wrote: >> >> On 09/07/

Re: [PATCH v7 0/4] VT-d minor fixes

Hi Michael, Yi and Jason Thanks for your feedback on the previous versions. If you agree with the series, do you think we can move forward? Thanks! >cmd On 09/07/2024 16:26, CLEMENT MATHIEU--DRIF wrote: > From: Clément Mathieu--Drif > > Various fixes for VT-d > > This ser

Re: [PATCH ats_vtd v5 20/22] pci: add a pci-level API for ATS

On 18/07/2024 01:44, Minwoo Im wrote: Caution: External email. Do not open attachments or click links, unless this email comes from a known sender and you know the content is safe. On 24-07-11 19:00:58, CLEMENT MATHIEU--DRIF wrote: On 11/07/2024 10:04, Minwoo Im wrote: Caution

Re: [PATCH v1 03/17] intel_iommu: Add a placeholder variable for scalable modern mode

On 18/07/2024 10:16, Zhenzhong Duan wrote: > Caution: External email. Do not open attachments or click links, unless this > email comes from a known sender and you know the content is safe. > > > Add an new element scalable_mode in IntelIOMMUState to mark scalable > modern mode, this element wil

Re: [PATCH v1 02/17] intel_iommu: Make pasid entry type check accurate

Reviewed-by: Clément Mathieu--Drif On 18/07/2024 10:16, Zhenzhong Duan wrote: > Caution: External email. Do not open attachments or click links, unless this > email comes from a known sender and you know the content is safe. > > > When guest configures Nested Translation(011b) or First-stage Tra

Re: [PATCH v1 15/17] intel_iommu: Set default aw_bits to 48 in scalable modren mode

Reviewed-by: Clément Mathieu--Drif On 18/07/2024 10:16, Zhenzhong Duan wrote: > Caution: External email. Do not open attachments or click links, unless this > email comes from a known sender and you know the content is safe. > > > According to VTD spec, stage-1 page table could support 4-level

Re: [PATCH v1 16/17] intel_iommu: Modify x-scalable-mode to be string option

On 18/07/2024 10:16, Zhenzhong Duan wrote: > Caution: External email. Do not open attachments or click links, unless this > email comes from a known sender and you know the content is safe. > > > From: Yi Liu > > Intel VT-d 3.0 introduces scalable mode, and it has a bunch of capabilities > rela

Re: [PATCH v1 03/17] intel_iommu: Add a placeholder variable for scalable modern mode

On 19/07/2024 04:47, Duan, Zhenzhong wrote: > Caution: External email. Do not open attachments or click links, unless this > email comes from a known sender and you know the content is safe. > > >> -Original Message- >> From: CLEMENT MATHIEU--DRIF >>

Re: [PATCH v1 16/17] intel_iommu: Modify x-scalable-mode to be string option

On 19/07/2024 04:53, Duan, Zhenzhong wrote: > Caution: External email. Do not open attachments or click links, unless this > email comes from a known sender and you know the content is safe. > > >> -Original Message- >> From: CLEMENT MATHIEU--DRIF >>

Re: [PATCH v1 03/17] intel_iommu: Add a placeholder variable for scalable modern mode

le modern mode >>> >>> On 2024/7/19 10:47, Duan, Zhenzhong wrote: >>>> >>>>> -Original Message- >>>>> From: CLEMENT MATHIEU--DRIF >>>>> Subject: Re: [PATCH v1 03/17] intel_iommu: Add a placeholder variable >>

Re: [PATCH v1 01/17] intel_iommu: Use the latest fault reasons defined by spec

Reviewed-by: Clément Mathieu--Drif On 18/07/2024 10:16, Zhenzhong Duan wrote: > Caution: External email. Do not open attachments or click links, unless this > email comes from a known sender and you know the content is safe. > > > From: Yu Zhang > > Spec revision 3.0 or above defines more detai

Re: [PATCH v1 03/17] intel_iommu: Add a placeholder variable for scalable modern mode

le modern mode >>> >>> On 2024/7/19 10:47, Duan, Zhenzhong wrote: >>>> >>>>> -Original Message- >>>>> From: CLEMENT MATHIEU--DRIF >>>>> Subject: Re: [PATCH v1 03/17] intel_iommu: Add a placeholder variable >>

Re: [PATCH v1 09/17] intel_iommu: Flush stage-1 cache in iotlb invalidation

Reviewed-by: Clément Mathieu--Drif On 18/07/2024 10:16, Zhenzhong Duan wrote: > Caution: External email. Do not open attachments or click links, unless this > email comes from a known sender and you know the content is safe. > > > According to spec, Page-Selective-within-Domain Invalidation (11b

Re: [PATCH v1 04/17] intel_iommu: Flush stage-2 cache in PADID-selective PASID-based iotlb invalidation

On 18/07/2024 10:16, Zhenzhong Duan wrote: > Caution: External email. Do not open attachments or click links, unless this > email comes from a known sender and you know the content is safe. > > > Per spec 6.5.2.4, PADID-selective PASID-based iotlb invalidation will > flush stage-2 iotlb entries

Re: [PATCH v1 10/17] intel_iommu: Process PASID-based iotlb invalidation

Reviewed-by: Clément Mathieu--Drif On 18/07/2024 10:16, Zhenzhong Duan wrote: > Caution: External email. Do not open attachments or click links, unless this > email comes from a known sender and you know the content is safe. > > > PASID-based iotlb (piotlb) is used during walking Intel > VT-d st

Re: [PATCH v1 04/17] intel_iommu: Flush stage-2 cache in PADID-selective PASID-based iotlb invalidation

On 24/07/2024 04:59, Duan, Zhenzhong wrote: > Caution: External email. Do not open attachments or click links, unless this > email comes from a known sender and you know the content is safe. > > >> -Original Message- >> From: CLEMENT MATHIEU--DRIF >>

Re: [PATCH v1 14/17] intel_iommu: piotlb invalidation should notify unmap

Maybe I'm missing something but why do we invalidate device IOTLB upon piotlb receipt of a regular IOTLB inv desc? I don't get why we don't wait for a device IOTLB inv desc? On 18/07/2024 10:16, Zhenzhong Duan wrote: > Caution: External email. Do not open attachments or click links, unless this >

Re: [PATCH v1 17/17] tests/qtest: Add intel-iommu test

On 18/07/2024 10:16, Zhenzhong Duan wrote: > Caution: External email. Do not open attachments or click links, unless this > email comes from a known sender and you know the content is safe. > > > Add the framework to test the intel-iommu device. > > Currently only tested cap/ecap bits correctnes

Re: [PATCH v1 14/17] intel_iommu: piotlb invalidation should notify unmap

On 24/07/2024 07:45, CLEMENT MATHIEU--DRIF wrote: > Maybe I'm missing something but why do we invalidate device IOTLB > upon piotlb receipt of a regular IOTLB inv desc? > I don't get why we don't wait for a device IOTLB inv desc? I thought you were planning to remove

Re: [PATCH v1 14/17] intel_iommu: piotlb invalidation should notify unmap

On 24/07/2024 08:07, Duan, Zhenzhong wrote: > Caution: External email. Do not open attachments or click links, unless this > email comes from a known sender and you know the content is safe. > > >> -Original Message- >> From: CLEMENT MATHIEU--DRIF >>

Re: [PATCH v1 11/17] intel_iommu: Extract device IOTLB invalidation logic

Hi Zhenzhong, This patch has been merged into staging this morning, be careful when re-sending your series. Here is the link : https://github.com/qemu/qemu/commit/6410f877f5ed535acd01bbfaa4baec379e44d0ef#diff-c19adbf518f644e9b651b67266802e14787292ab9d6cd4210b4f974585be6009 >cmd On 18/07/2024

Re: [PATCH v4 03/17] intel_iommu: Add a placeholder variable for scalable modern mode

LGTM, thanks for the update Reviewed-by: Clément Mathieu--Drif > Caution: External email. Do not open attachments or click links, unless this > email comes from a known sender and you know the content is safe. > > > Add an new element scalable_mode in IntelIOMMUState to mark scalable > modern

Re: [PATCH] intel_iommu: Remove Transient Mapping (TM) field from second-level page-tables

LGTM Thanks cmd > Caution: External email. Do not open attachments or click links, unless this > email comes from a known sender and you know the content is safe. > > > VT-d spec removed Transient Mapping (TM) field from second-level page-tables > and treat the field as Reserved(0) since revis

Re: [PATCH v2 2/8] chardev/chardev-internal: remove unused `max_size` struct member

Reviewed-by: Clément Mathieu--Drif On 14/10/2024 17:24, Roman Penyaev wrote: > Caution: External email. Do not open attachments or click links, unless this > email comes from a known sender and you know the content is safe. > > > Clean up forgotten leftovers. > > Signed-off-by: Roman Penyaev >

Re: [PATCH v2 3/8] chardev/mux: use bool type for `linestart` and `term_got_escape`

Reviewed-by: Clément Mathieu--Drif On 14/10/2024 17:24, Roman Penyaev wrote: > Caution: External email. Do not open attachments or click links, unless this > email comes from a known sender and you know the content is safe. > > > Those are boolean variables, not signed integers. > > Signed-off-

Re: [PATCH v2 7/8] chardev/mux: implement detach of frontends from mux

On 14/10/2024 17:24, Roman Penyaev wrote: > Caution: External email. Do not open attachments or click links, unless this > email comes from a known sender and you know the content is safe. > > > With bitset management now it becomes feasible to implement > the logic of detaching frontends from

Re: [PATCH 0/2] chardev/char-mux: tweak mux bitset operations

Hi Roman, Reviewed-by Clément Mathieu--Drif Thanks! On 02/11/2024 12:07, Roman Penyaev wrote: Caution: External email. Do not open attachments or click links, unless this email comes from a known sender and you know the content is safe. Patchset twe

[QUESTION/ISSUE] edk2 missing dependency

Hi everyone, It seems that https://github.com/Zeex/subhook (EDK2 submodule) is not longer available on github (which makes recursive pull of submodules fail for a lot of people). Do you think we should do something on our side? Thanks >cmd

Re: [PATCH 2/3] intel_iommu: Add missed sanity check for 256-bit invalidation queue

I saw the pull request, just a few questions/comments in case there is a new spin. These are not hard requirements, the current version looks good as well. On 04/11/2024 13:55, Zhenzhong Duan wrote: > Caution: External email. Do not open attachments or click links, unless this > email comes from

Re: [PATCH 3/3] intel_iommu: Add missed reserved bit check for IEC descriptor

Hi, lgtm Thanks cmd On 04/11/2024 13:55, Zhenzhong Duan wrote: > Caution: External email. Do not open attachments or click links, unless this > email comes from a known sender and you know the content is safe. > > > IEC descriptor is 128-bit invalidation descriptor, must be padded with > 128-

Re: [PATCH v4 04/17] intel_iommu: Flush stage-2 cache in PASID-selective PASID-based iotlb invalidation

On 04/11/2024 03:49, Yi Liu wrote: > Caution: External email. Do not open attachments or click links, unless > this email comes from a known sender and you know the content is safe. > > > On 2024/9/30 17:26, Zhenzhong Duan wrote: >> Per spec 6.5.2.4, PADID-selective PASID-based iotlb invalidat

Re: [PATCH v3 15/17] intel_iommu: Modify x-scalable-mode to be string option to expose scalable modern mode

On 04/11/2024 04:24, Yi Liu wrote: > Caution: External email. Do not open attachments or click links, > unless this email comes from a known sender and you know the content > is safe. > > > On 2024/9/29 10:44, Duan, Zhenzhong wrote >>> >>> A question here: >>> >>> Are there any other major featu

Re: [PATCH 2/3] intel_iommu: Add missed sanity check for 256-bit invalidation queue

On 05/11/2024 08:38, Duan, Zhenzhong wrote: > Caution: External email. Do not open attachments or click links, unless this > email comes from a known sender and you know the content is safe. > > >> -Original Message- >> From: CLEMENT MATHIEU--DRIF >> Sen

Re: [PATCH 1/3] intel_iommu: Send IQE event when setting reserved bit in IQT_TAIL

Hi, lgtm Thanks cmd On 04/11/2024 13:55, Zhenzhong Duan wrote: > Caution: External email. Do not open attachments or click links, unless this > email comes from a known sender and you know the content is safe. > > > According to VTD spec, Figure 11-22, Invalidation Queue Tail Register, > "When

Re: [PATCH v5] intel_iommu: Introduce property "stale-tm" to control Transient Mapping (TM) field

Reviewed-by: Clément Mathieu--Drif On 28/10/2024 03:25, Zhenzhong Duan wrote: > Caution: External email. Do not open attachments or click links, unless this > email comes from a known sender and you know the content is safe. > > > VT-d spec removed Transient Mapping (TM) field from second-level

Re: [PATCH v5 17/20] tests/acpi: q35: Update host address width in DMAR

Hi Zhenzhong, Ack >cmd On 11/11/2024 09:34, Zhenzhong Duan wrote: > Caution: External email. Do not open attachments or click links, unless this > email comes from a known sender and you know the content is safe. > > > Differences: > > @@ -1,39 +1,39 @@ > /* >* Intel ACPI Component Arch

Re: [PATCH v5 08/20] intel_iommu: Check stage-1 translation result with interrupt range

On 11/11/2024 09:34, Zhenzhong Duan wrote: > Caution: External email. Do not open attachments or click links, unless this > email comes from a known sender and you know the content is safe. > > > Per VT-d spec 4.1 section 3.15, "Untranslated requests and translation > requests that result in an a

[PATCH v1 17/19] intel_iommu: Set address mask when a translation fails and adjust W permission

From: Clément Mathieu--Drif Implements the behavior defined in section 10.2.3.5 of PCIe spec rev 5. This is needed by devices that support ATS. Signed-off-by: Clément Mathieu--Drif --- hw/i386/intel_iommu.c | 12 +--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/hw/i38

[PATCH v1 01/19] memory: Add permissions in IOMMUAccessFlags

From: Clément Mathieu--Drif This will be necessary for devices implementing ATS. We also define a new macro IOMMU_ACCESS_FLAG_FULL in addition to IOMMU_ACCESS_FLAG to support more access flags. IOMMU_ACCESS_FLAG is kept for convenience and backward compatibility. Here are the flags added (define

[PATCH v1 05/19] pcie: Add helper to declare PASID capability for a pcie device

From: Clément Mathieu--Drif Signed-off-by: Clément Mathieu--Drif --- hw/pci/pcie.c | 24 include/hw/pci/pcie.h | 6 +- include/hw/pci/pcie_regs.h | 5 + 3 files changed, 34 insertions(+), 1 deletion(-) diff --git a/hw/pci/pcie.c b/hw/pci/pci

[PATCH v1 09/19] pci: Add IOMMU operations to get memory regions with PASID

From: Clément Mathieu--Drif The region returned by this operation will be used as the input region for ATS. Signed-off-by: Clément Mathieu--Drif --- include/hw/pci/pci.h | 16 1 file changed, 16 insertions(+) diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h index 1356

[PATCH v1 14/19] atc: Add unit tests

From: Clément Mathieu--Drif Signed-off-by: Clément Mathieu--Drif --- tests/unit/meson.build | 1 + tests/unit/test-atc.c | 527 + 2 files changed, 528 insertions(+) create mode 100644 tests/unit/test-atc.c diff --git a/tests/unit/meson.build b/tests/

[PATCH v1 00/19] Rebase ATS onto lastest Qemu mailing list state

From: Clément Mathieu--Drif This series belongs to a list of series that add SVM support for VT-d. As a starting point, we use the series called 'intel_iommu: Enable stage-1 translation for emulated device' by Zhenzhong Duan and Yi Liu. Ref: https://github.com/yiliu1765/qemu/tree/zhenzhong/iomm

[PATCH v1 04/19] intel_iommu: Fill the PASID field when creating an IOMMUTLBEntry

From: Clément Mathieu--Drif PASID value must be used by devices as a key (or part of a key) when populating their ATC with the IOTLB entries returned by the IOMMU. Signed-off-by: Clément Mathieu--Drif --- hw/i386/intel_iommu.c | 9 + 1 file changed, 9 insertions(+) diff --git a/hw/i38

[PATCH v1 12/19] pci: Add a pci-level initialization function for iommu notifiers

From: Clément Mathieu--Drif We add a convenient way to initialize an device-iotlb notifier. This is meant to be used by ATS-capable devices. pci_device_iommu_memory_region_pasid is introduces in this commit and will be used in several other SVM-related functions exposed in the PCI API. Signed-o

[PATCH v1 11/19] memory: Store user data pointer in the IOMMU notifiers

From: Clément Mathieu--Drif This will help developers of svm devices to track a state Signed-off-by: Clément Mathieu--Drif --- include/exec/memory.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/exec/memory.h b/include/exec/memory.h index 756dd2ea7f..c0d064dbd8 100644 --- a/inclu

[PATCH v1 08/19] pci: Cache the bus mastering status in the device

From: Clément Mathieu--Drif The cached is_master value is necessary to know if a device is allowed to issue ATS requests or not. This behavior is implemented in an upcoming patch. Signed-off-by: Clément Mathieu--Drif --- hw/pci/pci.c| 25 +++-- include/hw/pc

[PATCH v1 07/19] pcie: Helper function to check if ATS is enabled

From: Clément Mathieu--Drif ats_enabled checks whether the capability is present or not. If so, we read the configuration space to get the status of the feature (enabled or not). Signed-off-by: Clément Mathieu--Drif --- hw/pci/pcie.c | 9 + include/hw/pci/pcie.h | 1 + 2 files

[PATCH v1 16/19] pci: Add a pci-level API for ATS

From: Clément Mathieu--Drif Devices implementing ATS can send translation requests using pci_ats_request_translation_pasid. The invalidation events are sent back to the device using the iommu notifier managed with pci_register_iommu_tlb_event_notifier and pci_unregister_iommu_tlb_event_notifier

[PATCH v1 06/19] pcie: Helper functions to check if PASID is enabled

From: Clément Mathieu--Drif pasid_enabled checks whether the capability is present or not. If so, we read the configuration space to get the status of the feature (enabled or not). Signed-off-by: Clément Mathieu--Drif --- hw/pci/pcie.c | 9 + include/hw/pci/pcie.h | 2 ++ 2 fil

[PATCH v1 10/19] intel_iommu: Implement the get_memory_region_pasid iommu operation

From: Clément Mathieu--Drif Signed-off-by: Clément Mathieu--Drif --- hw/i386/intel_iommu.c | 17 - include/hw/i386/intel_iommu.h | 2 +- 2 files changed, 17 insertions(+), 2 deletions(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index a92ef9fe74..7e867

[PATCH v1 19/19] intel_iommu: Add support for ATS

From: Clément Mathieu--Drif Signed-off-by: Clément Mathieu--Drif --- hw/i386/intel_iommu.c | 71 -- hw/i386/intel_iommu_internal.h | 1 + 2 files changed, 69 insertions(+), 3 deletions(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index

[PATCH v1 03/19] memory: Allow to store the PASID in IOMMUTLBEntry

From: Clément Mathieu--Drif This will be useful for devices that support ATS and need to store entries in an ATC (device IOTLB). Signed-off-by: Clément Mathieu--Drif --- include/exec/memory.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/exec/memory.h b/include/exec/memory.h inde

[PATCH v1 15/19] memory: Add an API for ATS support

From: Clément Mathieu--Drif IOMMU have to implement iommu_ats_request_translation to support ATS. Devices can use IOMMU_TLB_ENTRY_TRANSLATION_ERROR to check the tlb entries returned by a translation request. We decided not to use the existing translation operation for 2 reasons. First, ATS is d

[PATCH v1 13/19] atc: Generic ATC that can be used by PCIe devices that support SVM

From: Clément Mathieu--Drif As the SVM-capable devices will need to cache translations, we provide an first implementation. This cache uses a two-level design based on hash tables. The first level is indexed by a PASID and the second by a virtual addresse. Signed-off-by: Clément Mathieu--Drif

[PATCH v1 02/19] intel_iommu: Declare supported PASID size

From: Clément Mathieu--Drif PSS field of the ecap register stores the supported PASID size minus 1. Thus, this commit adds support for 20bits PASIDs. Signed-off-by: Clément Mathieu--Drif --- hw/i386/intel_iommu.c | 2 +- hw/i386/intel_iommu_internal.h | 1 + 2 files changed, 2 inserti

[PATCH v1 18/19] intel_iommu: Return page walk level even when the translation fails

From: Clément Mathieu--Drif We use this information in vtd_do_iommu_translate to populate the IOMMUTLBEntry and indicate the correct page mask. This prevents ATS devices from sending many useless translation requests when a megapage or gigapage iova is not mapped to a physical address. Signed-of

Re: [PATCH v5 18/20] intel_iommu: Introduce a property x-flts for scalable modern mode

Hi zhenzhong, Just one comment but you can add Reviewed-by: Clément Mathieu--Drif On 11/11/2024 09:34, Zhenzhong Duan wrote: > Caution: External email. Do not open attachments or click links, unless this > email comes from a known sender and you know the content is safe. > > > Intel VT-d 3.0 in

Re: [PATCH v5 18/20] intel_iommu: Introduce a property x-flts for scalable modern mode

On 19/11/2024 08:28, Duan, Zhenzhong wrote: Caution: External email. Do not open attachments or click links, unless this email comes from a known sender and you know the content is safe. Hi Clement, -Original Message- From: CLEMENT MATHIEU--DRIF <mailto:clement.mathieu

Re: [PATCH v5 15/20] tests/acpi: q35: allow DMAR acpi table changes

Hi, @Michael, are this patch and patch 17/20 ok for you? Thanks, cmd On 11/11/2024 09:34, Zhenzhong Duan wrote: > Caution: External email. Do not open attachments or click links, unless this > email comes from a known sender and you know the content is safe. > > > Signed-off-by: Zhenzhong Duan

Re: [PATCH v5 18/20] intel_iommu: Introduce a property x-flts for scalable modern mode

only available in scalable mode". Thanks Clement. From: CLEMENT MATHIEU--DRIF <mailto:clement.mathieu--d...@eviden.com> Sent: Tuesday, November 19, 2024 5:00 PM To: Duan, Zhenzhong <mailto:zhenzhong.d...@intel.com>; qemu-devel@nongnu.org<mailto:qemu-devel@nongnu.org> Cc

Re: [PATCH v5 08/20] intel_iommu: Check stage-1 translation result with interrupt range

On 13/11/2024 09:49, Duan, Zhenzhong wrote: > Caution: External email. Do not open attachments or click links, unless this > email comes from a known sender and you know the content is safe. > > >> -Original Message- >> From: CLEMENT MATHIEU--DRIF >> Sent

Re: [PATCH v5 18/20] intel_iommu: Introduce a property x-flts for scalable modern mode

On 04/12/2024 04:34, Jason Wang wrote: > Caution: External email. Do not open attachments or click links, unless this > email comes from a known sender and you know the content is safe. > > > On Mon, Nov 11, 2024 at 4:39 PM Zhenzhong Duan > wrote: >> >> Intel VT-d 3.0 introduces scalable mod

Re: [PATCH v5 18/20] intel_iommu: Introduce a property x-flts for scalable modern mode

On 09/12/2024 04:13, Jason Wang wrote: > Caution: External email. Do not open attachments or click links, unless this > email comes from a known sender and you know the content is safe. > > > On Wed, Dec 4, 2024 at 2:14 PM CLEMENT MATHIEU--DRIF > wrote: >> >> &g

Re: [PATCH for-10.0] tests/functional: Convert the intel_iommu avocado test

Hi Thomas, Reviewed-by: Clément Mathieu--Drif Thanks cmd On 06/12/2024 19:17, Thomas Huth wrote: > Caution: External email. Do not open attachments or click links, unless this > email comes from a known sender and you know the content is safe. > > > Convert the intel_iommu test to the new funct

Re: [PATCH v5 18/20] intel_iommu: Introduce a property x-flts for scalable modern mode

On 09/12/2024 07:24, Jason Wang wrote: > Caution: External email. Do not open attachments or click links, unless this > email comes from a known sender and you know the content is safe. > > > On Mon, Dec 9, 2024 at 2:15 PM CLEMENT MATHIEU--DRIF > wrote: >> >>

Re: [PATCH v1 04/19] intel_iommu: Fill the PASID field when creating an IOMMUTLBEntry

Hi zhenzhong, On 23/12/2024 06:50, Duan, Zhenzhong wrote: > Caution: External email. Do not open attachments or click links, unless this > email comes from a known sender and you know the content is safe. > > > Hi Clement, > >> -Original Message- >&g

Re: [PATCH v5 18/20] intel_iommu: Introduce a property x-flts for scalable modern mode

nt, >> >> Sorry for late reply, just back from vacation. >> >>> -----Original Message- >>> From: CLEMENT MATHIEU--DRIF >>> Subject: Re: [PATCH v5 18/20] intel_iommu: Introduce a property x-flts for >>> scalable modern mode >>> >

Re: [PATCH v2] tests/functional: Convert the intel_iommu avocado test

Hi Thomas, 2 minor comments but LGTM On 10/12/2024 13:56, Thomas Huth wrote: Caution: External email. Do not open attachments or click links, unless this email comes from a known sender and you know the content is safe. Convert the intel_iommu test to the new functional framework. This test n

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